PHY Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 17 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $242k

$131k most similar roles pay here $327k

This role pays more than 85% of similar roles. Most pay $168,500–$227,900 — the shaded band above. At the midpoint, this role pays about $242k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · PHY Design Verification Engineer

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As a PHY Design Verification Engineer, you will join the wireless silicon development team to perform pre-silicon RTL verification of wireless PHY and its interfaces with the broader communication SoC. You will collaborate with DV methodologists, designers, and systems engineers to develop reusable test benches and verification environments using metric-driven methodologies. Your daily responsibilities include creating verification plans from specifications, executing directed and constrained random tests, managing bug tracking, and analyzing coverage models. The role requires expertise in Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with proficiency in Python, shell, and Perl scripting. You will also utilize Matlab/C reference models for bit-accurate verification and leverage AI technologies for data mining. Additionally, you will support PHY subsystem validation using Palladium and FPGA hardware to ensure high design quality for wireless communication protocols like Bluetooth, UWB, WLAN, or Zigbee.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Bluetooth WLAN Zigbee UWB

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets.
Build reusable block and subsystem test benches using best-in-class DV methodologies.
Develop and execute directed and constrained random tests for RTL verification.
Debug failures, manage bug tracking, and work with designers to resolve issues.
Create and analyze coverage models while adding test cases to increase coverage.
Utilize machine learning and AI technologies to identify design and test bench issues.
Support PHY subsystem validation using Palladium or FPGA platforms.
Improve overall DV methodology and flow through collaboration with team members.

What we're looking for

Bachelor of Science degree.
Minimum of 10 years of relevant industry experience.
Experience verifying wireless or wired communication blocks and subsystems (preferred).
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions (preferred).
Experience with ASIC verification flows including test bench development, constrained random testing, and coverage (preferred).
Proficiency in shell, Python, and Perl scripting (preferred).
Experience using Matlab/C reference models and bit-accurate verification (preferred).
Knowledge of wireless protocols like Bluetooth, UWB, WLAN, or Zigbee; AI technologies; and Palladium/FPGA validation (preferred).

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