Verification Engineer

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, CO
Salary
$121,900–$195,000 / yr
Employment
Full-time
Posted
106 days ago
Freshness
Confirmed live today
Closes
Jan 9, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $209k
This role $158k
$108k $256k
below market most similar roles pay here above market

This role pays less than 87% of similar roles. Most pay $177,200–$241,750 — the blue band above. At the midpoint, this role pays about $158k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Verification Engineer

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The Verification Engineer joins the ASIC Product Division to ensure the quality of complex intellectual property for cloud computing, networking, and wireless solutions. This role involves developing and executing verification plans for IP blocks at both block and system levels. Key responsibilities include building and maintaining System Verilog and UVM-based verification environments, developing Python-based behavioral models, and validating designs against RTL implementations. The engineer will analyze simulation results, debug failures, and develop automation scripts or regression frameworks. Required technical skills include proficiency in System Verilog, UVM/OVM, Python, C/C++, and scripting. The position requires expertise in RTL verification methodologies and ASIC flows to solve complex verification trade-offs. Candidates may also utilize AI-assisted tools like ChatGPT and Gemini to enhance overall productivity.

Skills

System Verilog UVM OVM Python C C++ RTL ASIC Verification Scripting Formal Verification Firmware Embedded C DSP DDR Network Protocols AI-assisted tools

What you'll do

  • Develop and execute verification plans for IP blocks at both block and system levels.
  • Build and maintain System Verilog/UVM-based verification environments and testbenches.
  • Develop Python-based behavioral models and validate designs against RTL implementations.
  • Analyze simulation results and debug failures to drive root-cause resolution.
  • Develop and maintain automation scripts and regression frameworks.
  • Improve verification methodologies and flows to enhance design quality.
  • Leverage AI-assisted tools to increase verification productivity.

What we're looking for

  • Bachelor’s degree in Electrical/Electronic Engineering or Computer Science.
  • 8+ years of relevant industry experience.
  • Strong expertise in RTL verification methodologies.
  • Experience with ASIC verification flows and design verification methodologies.
  • Proficiency in UVM/OVM, Python, C/C++, and scripting.
  • Experience with block-level and system-level verification.
  • Experience with firmware development or embedded C (preferred).
  • Knowledge of PHY layers, formal verification, or CPU, DDR, and network protocols (preferred).

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