Verification Engineer

Broadcom

Quick summary

Work type: On-site
Location: San Jose, CA · Fort Collins, CO
Salary: $120,000–$192,000 / yr
Posted: 24 days ago
Closes: Nov 9, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $171k

This role $156k

$109k most similar roles pay here $223k

This role pays less than 58% of similar roles. Most pay $141,562–$199,625 — the shaded band above. At the midpoint, this role pays about $156k versus about $171k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 105 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 103 roles with salary data.

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At a glance

TL;DR · Verification Engineer

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As a senior verification engineer at Broadcom’s ASIC Product Division (APD), you will develop and execute verification plans for IP blocks at both block and system levels, building and maintaining System Verilog/UVM-based verification environments and testbenches. Your daily tasks include developing Python-based behavioral models to validate designs against RTL implementations, analyzing simulation results, debugging failures, and driving root-cause resolution. You will collaborate closely with design, architecture, and verification teams to ensure high-quality design outputs while also contributing to the improvement of verification methodologies and flows. Key skills required are expertise in RTL verification methodologies, proficiency in UVM/OVM, Python, C/C++, and scripting, as well as experience with block-level and system-level verification. The role leverages AI-assisted tools like ChatGPT and Gemini to enhance productivity within a large-scale semiconductor environment focused on delivering cutting-edge technology platforms for diverse industries.

Skills

SystemVerilog UVM Python C/C++ ASIC verification flows block-level verification system-level verification formal verification methodologies firmware development embedded C PHY layers adaptation techniques CPU DDR bus protocols network protocols DSP design AI-assisted tools

What you'll do

Develop and execute verification plans for IP blocks at both block and system levels.
Build and maintain System Verilog/UVM-based verification environments and testbenches.
Analyze simulation results, debug failures, and drive root-cause resolution.
Contribute to the improvement of verification methodologies and flows.
Develop Python-based behavioral models and validate designs against RTL implementations.

What we're looking for

8+ years of experience in ASIC verification
Expertise in RTL verification methodologies using System Verilog
Proficiency in UVM/OVM, Python, C/C++, and scripting languages
Experience with block-level and system-level verification processes
Strong debugging skills and ability to resolve complex issues
Contribution to the development and maintenance of automation scripts
Collaboration with design, architecture, and verification teams

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