Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CAFort Collins, CO
Salary: $143,800–$230,000 / yr
Posted: 47 days ago
Freshness: Confirmed live yesterday
Closes: Nov 9, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $186k

This role $187k

$125k most similar roles pay here $241k

This role pays more than 60% of similar roles. Most pay $158,862–$212,500 — the shaded band above. At the midpoint, this role pays about $187k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · Verification Engineer

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As a Verification Engineer within the ASIC Product Division, you will develop and execute verification plans for IP blocks at both block and system levels. You will build and maintain System Verilog and UVM-based verification environments and testbenches while developing Python-based behavioral models to validate designs against RTL implementations. Your daily responsibilities include analyzing simulation results, debugging failures, driving root-cause resolutions, and creating automation scripts for regression frameworks. To succeed, you must possess expertise in RTL verification methodologies, System Verilog, UVM/OVM, Python, C/C++, and scripting. You will also utilize AI-assisted tools like ChatGPT or Cursor to enhance productivity. This role focuses on the technical challenge of ensuring design quality for complex integrated circuit components, specifically addressing hardware verification flows and solving intricate trade-offs within the semiconductor product space.

Skills

System Verilog UVM OVM Python C C++ RTL Verification Scripting Firmware Formal Verification DSP PHY DDR Network Protocols AI-assisted tools

What you'll do

Develop and execute verification plans for IP blocks at both block and system levels.
Build and maintain System Verilog/UVM-based verification environments and testbenches.
Develop Python-based behavioral models to validate designs against RTL implementations.
Analyze simulation results, debug failures, and drive root-cause resolution.
Develop and maintain automation scripts and regression frameworks.
Improve verification methodologies and flows.
Utilize AI-assisted tools to enhance engineering productivity.

What we're looking for

Bachelor's degree in Electrical/Electronic Engineering or Computer Science.
12+ years of relevant industry experience.
Strong expertise in RTL verification methodologies and System Verilog.
Proficiency in UVM/OVM, Python, C/C++, and scripting.
Experience with ASIC verification flows and design verification methodologies.
Experience with block-level and system-level verification.
Strong debugging, problem-solving, and communication skills.
Familiarity with AI-assisted development tools to enhance productivity.