Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, CO
Employment
Full-time
Posted
92 days ago
Freshness
Confirmed live yesterday
Closes
Nov 9, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $209k
$139k $253k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $176,493–$241,750.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Verification Engineer

Role Posting Log in to save

JOB TITLE: Verification Engineer The Verification Engineer joins the ASIC Product Division to ensure the quality of complex intellectual property for cloud computing AI engines, supercomputers, networking, and wireless solutions. This role involves developing and executing verification plans for IP blocks at both block and system levels. Key responsibilities include building and maintaining SystemVerilog and UVM-based verification environments, developing Python-based behavioral models, and validating designs against RTL implementations. The engineer will analyze simulation results, debug failures, and drive root-cause resolution while maintaining automation scripts and regression frameworks. Required technical skills include proficiency in SystemVerilog, UVM/OVM, Python, C/C++, and RTL verification methodologies. Candidates should also possess experience with ASIC verification flows, debugging complex trade-offs, and utilizing AI-assisted tools like ChatGPT, Gemini, and Cursor to enhance productivity.

Skills

System Verilog UVM OVM Python C C++ RTL Verification ASIC Verification Formal Verification Embedded C Scripting Regression Frameworks PHY layers DSP CPU DDR Network Protocols AI-assisted tools

What you'll do

  • Develop and execute verification plans for IP blocks at both block and system levels.
  • Build and maintain SystemVerilog and UVM-based verification environments and testbenches.
  • Develop Python-based behavioral models and validate designs against RTL implementations.
  • Analyze simulation results and debug failures to drive root-cause resolution.
  • Develop and maintain automation scripts and regression frameworks.
  • Contribute to the improvement of verification methodologies and flows.
  • Leverage AI-assisted tools to enhance verification productivity.

What we're looking for

  • Bachelor’s degree in Electrical/Electronic Engineering or Computer Science.
  • 12+ years of relevant industry experience.
  • Strong expertise in RTL verification methodologies, including SystemVerilog.
  • Experience with ASIC verification flows and design verification methodologies.
  • Proficiency in UVM/OVM, Python, C/C++, and scripting.
  • Experience with block-level and system-level verification.
  • Experience with firmware development or embedded C (preferred).
  • Knowledge of PHY layers, formal verification, or CPU/DDR/network protocols (preferred).

Related searches

More Verification Engineer jobs Verification Engineer jobs in San Jose All jobs at Broadcom

More like this

Similar roles

Verification Engineer

Broadcom

San Jose, CA +1 106 days ago $121,900–$195,000
System Verilog UVM OVM Python C C++ RTL ASIC Verification Scripting Formal Verification Firmware Embedded C DSP DDR Network Protocols AI-assisted tools
8+ yrs exp
Save

Design Verification Engineer

Broadcom

San Jose, CA 130 days ago $143,800–$230,000
System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators C Scripting DSP Design Coverage Assertions
10+ yrs exp
Save

Design Verification Engineer

Broadcom

San Jose, CA 130 days ago $143,800–$230,000
System Verilog UVM OVM C++ SystemC Perl ASIC Design Verification RTL Verification FPGA Emulators Coverage Assertions C Scripting
10+ yrs exp
Save

Design Verification Engineer

Amd

Santa Clara, CA 90 days ago $136,000–$204,000
System Verilog Verilog UVM C C++ Python Perl TCL ASIC Design Verification RTL Firmware DDR Memory Controller PHY Verification Functional Verification Code Coverage Simulation Tools
Save

Design Verification Engineer

Broadcom

Broomfield, CO +4 84 days ago $143,800–$230,000
SystemVerilog UVM SVA RTL Gate-level Netlist Python Perl Tcl FPGA Emulation Synopsys Cadence Mentor Git DesignSync Mixed-Signal SDF Co-simulation
10+ yrs exp
Save

Design Verification Engineer

Apple Inc

Cupertino, CA 54 days ago $155,896–$225,300
System Verilog UVM C C++ Python Perl EDA Tools Digital Design Computer Architecture Constrained Random Verification Functional Coverage ASIC Design Flow High-speed Interface Protocols Regression Analysis Verification IP
3+ yrs exp
Save