Design Verification Engineer

What you'll do

• Create comprehensive test plans based on design specifications and micro-architecture.
• Develop scalable and portable verification environments using SystemVerilog and UVM.
• Build verification components including stimulus, checkers, assertions, trackers, and coverage.
• Execute verification plans for design bring-up and regression enabling.
• Debug test failures and fix bugs identified during regression cycles.
• Track and report verification progress using bugs and coverage metrics.
• Utilize LLMs and related technologies to improve verification efficiency and quality.
• Manage all phases of pre-silicon verification for RTL freeze and tape-out.

What we're looking for

• BS degree in a technical subject area.
• Minimum of 10 years of relevant industry experience.
• Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
• Deep knowledge in developing scalable and portable test-benches (preferred).
• Strong experience with verification methodologies and tools such as simulators, waveform viewers, and coverage collection (preferred).
• Working experience using LLMs for efficiency and quality (preferred).
• Experience with power-aware (UPF) or similar verification methodology (preferred).
• Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).