Staff DFx Methodology Architect

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
26 days ago
Freshness
Confirmed live today
Closes
Aug 6, 2027
Nearby
99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $204k
This role $208k
$137k $272k
below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $175,218–$233,050 — the blue band above. At the midpoint, this role pays about $208k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Staff DFx Methodology Architect

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The Staff DFx Methodology Architect joins the AECG organization to serve as an expert in DFx architecture, methodology, and logic design. This role focuses on supporting FPGA-SoCs and custom ASICs by owning the definition of SoC-DFx architecture, specifications, and the development of DFx-IPs. Daily responsibilities include implementing features in RTL, managing documentation for hardware and firmware interactions, and co-owning timing and design quality checks. The candidate must utilize Verilog, SystemVerilog, and scripting languages like Perl, Python, and TCL. Technical proficiency in Siemens Tessent DFT flows, 1149.1/1687 standards, and ATPG is required. The role involves solving complex problems regarding power, performance, and area while driving innovation in front-end, DFx, and timing methodologies to ensure successful silicon bring-up and debug.

Skills

RTL Verilog SystemVerilog DFT FPGA ASIC Siemens Tessent ATPG IJTAG Python Perl TCL Logic Design Silicon Debug 1149.1 1687 3D IC Testing

What you'll do

  • Define and lead SoC-DFx architecture, specifications, and the development of DFx-IPs.
  • Own DFx architecture documentation, including interactions with hardware, firmware, and other features.
  • Implement DFx features in RTL using Verilog and SystemVerilog.
  • Co-own timing and design quality checks and waivers for DFx-IPs.
  • Work with execution and verification teams to integrate and validate DFx-IPs throughout the design flow.
  • Review verification test plans, timing targets, and performance/power verification sign-offs with design teams.
  • Engage with validation and product teams on test plans, coverage, silicon bring-up, and silicon debug.
  • Contribute to the development of front-end, DFx, and timing methodologies.

What we're looking for

  • Bachelor's, Master's, or PhD degree in Computer or Electrical Engineering.
  • Significant success driving Architecture, Design Methodologies, RTL, and Timing to tape out and production.
  • Experience implementing DFx features in RTL using Verilog/SystemVerilog.
  • Ability to define and lead SoC-DFx Architecture, specifications, and development of DFx-IPs.
  • Proficiency with Siemens Tessent DFT flows such as Tessent Shell, Scan, ATPG, MemoryBist, IJTAG, and SSN (preferred).
  • Understanding of 1149.1 / 1687 standards, ATPG, and experience in 2.5D and 3D IC testing (preferred).
  • Strong foundation in logic design, switching theory, timing, and DFT Architecture/Debug methodologies (preferred).
  • Experience with scripting languages including Perl, Python, and TCL (preferred).

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