DFT Architect

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$232,000–$348,000 / yr
Posted
11 days ago
Freshness
Confirmed live yesterday
Closes
Aug 31, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $211k
This role $290k
$128k most similar roles pay here $372k

This role pays more than 88% of similar roles. Most pay $174,975–$246,925 — the shaded band above. At the midpoint, this role pays about $290k versus about $211k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · DFT Architect

Role Posting Log in to save

As a DFT Architect, you will join the global quality and operation organization to drive DFT architecture definitions for future products including Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers, and FPGA logics. You will manage activities across architecture, design implementation, verification, and test implementation while ensuring structures are correctly implemented to meet specifications. The role involves promoting ATE and production test environments, improving test cost and quality, and planning for diagnosability and yield improvement. You will utilize tools such as ATPG, scan compression, and Tessent Streaming Scan Network SSN while applying knowledge of Verilog, synthesis, physical implementation, STA, and firmware-driven test solutions. This role solves manufacturing test challenges by overseeing early architecture design through successful silicon high-volume production for complex chip-level designs including SoC level integration and post-silicon debug.

Skills

DFT Scan MBIST ATPG Scan Compression Verilog Tessent Streaming Scan Network STA FPGA Firmware Post-Silicon Debug Oscilloscope Synthesis High-speed IO PHY Digital Communication

What you'll do

  • Define DFT architectures for Scan, MBIST, PHY, high-speed IOs, and communication controllers for future products.
  • Drive ATE and production test environment improvements to optimize test cost and quality.
  • Manage DFT activities across architecture, design implementation, verification, and test implementation phases.
  • Ensure DFT structures are correctly implemented by collaborating with design and physical design teams.
  • Lead internal teams to develop and implement effective firmware-driven test solutions.
  • Plan for system diagnosability and yield improvement throughout the product lifecycle.
  • Oversee the transition from early architecture definition to successful high-volume silicon production.

What we're looking for

  • MS or Ph.D. in Electrical, Electronic, or Computer Engineering.
  • Significant DFT engineering experience through pre and post silicon cycles.
  • Experience creating and implementing complex chip-level DFT architecture.
  • Experience with Scan, Scan Compression at IP/SoC levels, and ATPG (Stuck-At, At-Speed, Path-Delay).
  • Strong MBIST knowledge and experience with PHY, high-speed IO, and digital communication.
  • Understanding of Verilog, synthesis, physical implementation, STA, and verification methodology.
  • Experience with post-silicon debug and bench equipment like oscilloscopes and logic analyzers.
  • Ability to communicate complex engineering subjects effectively to cross-functional teams and management.

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