DFT Architect

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $232,000–$348,000 / yr
Posted: 57 days ago
Freshness: Confirmed live today
Closes: Aug 31, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $208k

This role $290k

$137k $371k

below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $165,187–$250,000 — the blue band above. At the midpoint, this role pays about $290k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · DFT Architect

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The DFT Architect will join the global quality and operation organization to drive DFT architecture definitions for future products. This role involves overseeing early architecture design definitions through successful silicon high-volume production, focusing on Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers, and FPGA logics. The architect will manage DFT activities across architecture, design implementation, verification, and test implementation while promoting ATE and production test environment enhancements. Key responsibilities include planning for diagnosability, yield improvement, and firmware-driven test solutions. Required technical skills include experience with Scan Compression, ATPG, MBIST, and tools like Tessent Streaming Scan Network SSN. Candidates must demonstrate proficiency in Verilog, synthesis, physical implementation, STA, and verification methodology, alongside experience with post-silicon debug using oscilloscopes and logic analyzers.

Skills

DFT Scan Compression MBIST ATPG Verilog Tessent Streaming Scan Network SSN STA FPGA Post-Silicon Debug Oscilloscope Logic Analyser Synthesis Physical Design Firmware Digital Communication PHY High-Speed IO

What you'll do

Define DFT architectures for Scan, MBIST, PHY, high-speed IOs, and communication controllers.
Manage DFT activities across architecture, design implementation, verification, and test implementation for new products.
Drive internal teams to correctly implement and create test solutions.
Develop firmware-driven test solutions for future products.
Plan for silicon diagnosability and yield improvement.
Ensure DFT structures are correctly implemented by working closely with design teams.
Oversee early architecture design definitions through to successful high-volume silicon production.
Promote ATE and production test environment enhancements to improve test cost and quality.

What we're looking for

MS or Ph.D. in Electrical/Electronic/Computer Engineering.
Significant DFT engineering experience through DFT pre and post silicon cycles (preferred).
Experience in creating and implementing complex chip-level DFT architecture (preferred).
Experience in DFT implementation including Scan and Scan Compression at IP and SoC level (preferred).
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression (preferred).
Strong MBIST knowledge (preferred).
Experience in PHY, high-speed IO, digital communication and functional test development (preferred).
Good understanding of Verilog, synthesis, physical implementation, STA, and verification methodology (preferred).

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