below marketmost similar roles pay hereabove market
This role pays more than
98%
of similar roles. Most pay
$177,287–$236,487
— the blue band above.
At the midpoint, this role pays about
$290k
versus about
$207k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
496 open roles
on FindRole.
Listed pay typically runs
$172,000–$258,000
across 496 roles with salary data.
The DFT/DFx Architecture & RTL Lead joins the Circuit Technology team to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs. This role involves leading DFT/DFx architecture definition, RTL implementation, and methodology development for advanced PHY and connectivity IP designs. Key responsibilities include implementing features in Verilog and SystemVerilog, developing scan architectures, and supporting JTAG/IJTAG, ICL/PDL, and scan compression. The candidate will utilize Siemens Tessent-based flows, Synopsys VCS, and Verdi for gate-level simulation, debug, and ATPG pattern generation. Core tasks involve managing test constraints, MBIST features, and lint analysis to ensure production-ready IP. The position requires solving complex technical problems related to scan-readiness, test coverage, and silicon bring-up for high-performance and low-power digital designs across SoCs.
Define and lead DFT/DFx architecture and methodology for high-speed SerDes, Memory PHY, and die-to-die interconnect IPs.
Implement DFT/DFx features in RTL using Verilog and SystemVerilog.
Develop micro-architectures for scan, test modes, clocking, reset, isolation, and observability features.
Support JTAG/IJTAG, ICL/PDL, scan compression, and hierarchical DFT implementation.
Execute ATPG flows including pattern generation, validation, and debug using Siemens Tessent or equivalent tools.
Develop and maintain DFT timing constraints, test-mode constraints, and integration guidelines.
Perform gate-level simulation and debug using Synopsys VCS and Verdi.
Partner with engineering teams on silicon bring-up, tester pattern debug, and yield-learning activities.
What we're looking for
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant technical education and industry experience.
Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology (preferred).
Hands-on RTL coding experience in Verilog and/or SystemVerilog (preferred).
Experience with Siemens Tessent DFT flows or comparable industry-standard DFT tools and methodologies (preferred).
Experience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies (preferred).
Experience with industry-standard ATPG, scan insertion, and DFT implementation tools (preferred).
Experience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs (preferred).
Experience analyzing DFT readiness, lint, controllability, observability, and test coverage issues (preferred).