SIPI Engineer, Senior

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$133,900–$200,900 / yr
Posted
19 days ago
Freshness
Confirmed live yesterday
Closes
Mar 21, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $167k
$121k $258k
below market most similar roles pay here above market

This role pays less than 74% of similar roles. Most pay $167,175–$230,750 — the blue band above. At the midpoint, this role pays about $167k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 558 open roles on FindRole.

Listed pay typically runs $152,130–$222,500 across 534 roles with salary data.

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At a glance

TL;DR · SIPI Engineer, Senior

The SIPI Engineer, Sr. joins the Packaging Engineering group to support the Central Hardware System for next-generation server projects. This role focuses on optimizing overall system performance by collaborating with IC, Package, and PBC designers. Key responsibilities include ensuring system-level constraints are met prior to package Tape-out, performing package extraction for time and frequency domain analysis, and conducting system-level analysis for DDR, SerDes, and PDN. The engineer will develop design guidelines for Package and PCB design while creating technical documentation. Required skills include expertise in Electromagnetics, transmission line theory, and crosstalk. Candidates must be proficient in field solvers like HFSS, Q3D, Sentinel-PSI, and Clarity, as well as simulation tools like ADS and Hspice, alongside experience with Cadence Allegro, Mentor Xpedition, and Matlab.

What you'll do

  • Perform package extraction for time domain and frequency domain analysis.
  • Conduct system-level analysis for DDR, SerDes, and PDN.
  • Develop design guidelines for Package and PCB design.
  • Ensure all system-level constraints are met prior to package Tape-out.
  • Assess the impact of ball assignment on system-level performance.
  • Communicate with PHY owners to understand specifications for various IPs.
  • Create technical documentation and presentations.

What we're looking for

  • Bachelor's degree in Chemical, Electrical, or Mechanical Engineering and 2+ years of relevant experience.
  • Master's degree in Chemical, Electrical, or Mechanical Engineering and 1+ year of relevant experience.
  • PhD in Chemical, Electrical, or Mechanical Engineering.
  • 3+ years of experience in DDR/SerDes in Package/PCB/System Design related to compute, Auto, and/or Server projects (preferred).
  • Experience in Electromagnetics and solid background on transmission line theory and Crosstalk (preferred).
  • Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity (preferred).
  • Experience in simulation tools such as ADS and Hspice (preferred).
  • Working knowledge in Cadence Allegro/APD/Sip or Mentor Xpedition (preferred).

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