Senior Staff Packaging SIPI Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $180,400–$270,600 / yr
Posted: 56 days ago
Freshness: Confirmed live yesterday
Closes: Jan 13, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k

This role $226k

$131k most similar roles pay here $286k

This role pays more than 80% of similar roles. Most pay $155,900–$216,250 — the shaded band above. At the midpoint, this role pays about $226k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior Staff Packaging SIPI Engineer

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The Packaging SIPI Engineer, Sr. Staff joins the Package Electrical Team to optimize package designs through signal and power integrity analysis. This leadership role involves collaborating with IC designers, PHY owners, and PCB designers to ensure system-level constraints are met before tape-out. Key responsibilities include performing time and frequency domain extractions, conducting system-level analysis for DDR, SerDes, and mixed-signal interfaces, and developing automated design flows. The candidate will provide technical guidance on ball assignment impacts and create documentation for various IPs like LPDDR, PCIe, UFS, USB, and MIPI. Required expertise includes transmission line theory, crosstalk, and electromagnetics. Technical proficiency is required in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity, alongside simulation tools like ADS and Hspice. Experience with Matlab, C/C++, Python, Perl, and Cadence Allegro tools is highly valued for automation.

Skills

Signal Integrity Power Integrity SerDes PCIe LPDDR UFS USB MIPI Matlab C++ Python Perl HFSS Q3D Sentinel-PSI Clarity ADS Hspice Cadence Allegro Mentor Xpedition

What you'll do

Perform package extraction for time domain and frequency domain analysis.
Conduct system-level analysis for DDR, SerDes, and mixed-signal interfaces.
Provide technical design guidelines for package optimization to internal teams.
Execute system simulations to ensure all constraints are met before tape-out.
Develop and automate design and analysis workflows.
Lead a team of engineers across multiple international locations.
Create technical documentation and presentations for management decision-making.

What we're looking for

Bachelor's degree with 6+ years of experience, Master's with 5+ years, or PhD with 4+ years in engineering or related fields.
Experience in system/package design, technology engineering, or related work.
Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity.
Experience with simulation tools like ADS and Hspice.
Working knowledge of Cadence Allegro/APD/Sip or Mentor Xpedition.
Experience in SerDes design specifications including PCIe Gen-x, USB, and UFS for server designs.
Proficiency in Matlab for automation or programming languages such as C, C++, Perl, or Python.
Prior management experience and ability to lead engineers across multiple international geographies.

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