Package Design Engineer, Staff

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$154,000–$231,000 / yr
Posted
50 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 19, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $192k
$143k most similar roles pay here $245k

This role pays less than 54% of similar roles. Most pay $170,000–$222,000 — the shaded band above. At the midpoint, this role pays about $192k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Package Design Engineer, Staff

Package Design Engineer - Staff works within the Data Center team to develop high-performance, energy-efficient server solutions for data center applications. The role involves owning advanced package selection, product structure configuration, and physical design for SoC packages and modules. Key responsibilities include managing layout optimization, tape-out processes, and coordinating with multi-functional teams to achieve optimal mechanical, electrical, and thermal performance. The candidate will develop design verification strategies, optimize pinouts, and ensure SI/PI requirements are met while exploring new CAD tools. Required technical skills include proficiency in Cadence APD, SiP, or Siemens Xpedition Package Designer, along with experience in DFM, DRC, and ERC. Knowledge of high-speed interfaces like DDR, PCIe, and UCIE is essential, alongside familiarity with advanced configurations such as Flip chip BGA and 2.5D/3D Interposer technologies to solve complex integration challenges.

What you'll do

  • Own and drive advanced package selection, new generation product structure, and configuration optimization.
  • Perform physical design, layout, and tape-out for Package/SiP designs.
  • Optimize mechanical, electrical, and thermal performance for various chip types.
  • Develop design verification and automation strategies to streamline package design and release flows.
  • Ensure package designs meet specific signal integrity (SI) and power integrity (PI) requirements.
  • Drive methodology improvements and feature development in collaboration with vendors and developers.
  • Evaluate and develop new CAD tools and verification flows for package design.
  • Partner with product teams to optimize chip floorplans, bump placement, and overall package size.

What we're looking for

  • Master's degree in electrical engineering, mechanical engineering, material science, or a related field.
  • 5+ years of experience in the electrical, material, thermal, or mechanical engineering fields.
  • Proficiency in Cadence APD & SiP and/or Siemens Xpedition Package Designer (xPD).
  • Experience with package design using Cadence Allegro platform tools including PCB Editor and Advanced Package Designer.
  • Knowledge of IC packaging structures, chip-package interactions, and substrate manufacturing processes.
  • Basic knowledge of signal integrity for high-speed IO interfaces and electromagnetic field theory.
  • Understanding of high-speed interfaces such as DDR, PCIe, and UCIE.
  • Familiarity with advanced package configurations like Flip chip BGA and 2.5D/3D Interposer.

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