Package Design Engineer - Staff

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$160,200–$240,200 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $208k
This role $200k
$148k $266k
below market most similar roles pay here above market

This role pays less than 56% of similar roles. Most pay $177,300–$237,912 — the blue band above. At the midpoint, this role pays about $200k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Package Design Engineer - Staff

The Package Design Engineer - Staff joins the Data Center team to develop high-performance, energy-efficient server solutions. This role involves owning advanced package selection, new generation product package structures, and configuration optimization. The engineer will perform physical design, layout, and tape-out for packages and modules, while coordinating with multi-functional groups to optimize mechanical, electrical, and thermal performance. Key responsibilities include defining design verification strategies, optimizing pin out, and managing SI/PI requirements. Candidates must be proficient in Cadence APD & SiP or Siemens Xpedition Package Designer, with experience in Constraint Manager, DRC checking, and DFM verification. Technical expertise is required in high-speed IO interfaces like DDR and PCIe, as well as knowledge of flip chip BGA, 2.5D/3D Interposer, and substrate manufacturing processes.

What you'll do

  • Own and drive advanced package selection, product structure, and configuration optimization.
  • Perform physical design, layout, design verification, and tape-out for packages and SiPs.
  • Optimize mechanical, electrical, and thermal performance for various chip types.
  • Define and develop design verification and automation strategies to streamline release flows.
  • Ensure package designs meet specific signal integrity and power integrity requirements.
  • Develop new CAD tools and verification flows to improve design efficiency.
  • Optimize chip floorplans, bump placements, and overall package size.

What we're looking for

  • Master's degree in electrical engineering, mechanical engineering, material science, or related fields with 5+ years of experience (preferred).
  • Proficient in Cadence APD & SiP and/or Siemens Xpedition Package Designer (xPD).
  • Knowledge of IC packaging structures, chip-package, and package-board interaction.
  • Basic knowledge of signal-integrity for high-speed IO interfaces, transmission line, and electromagnetic field theory.
  • Experience in using in-line DRC checking, DFM verification, and Electrical Rule Checking (ERC) (preferred).
  • Basic knowledge of electronic packaging process and typical failure modes (preferred).
  • Familiarity with various sophisticated package configurations and assembly/substrate technology (preferred).
  • Experience in package design and proficiency in Cadence Allegro platform tools (preferred).

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