Senior ASIC Hardware Design Engineer

Nvidia

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Westford, MA
Employment
Full-time
Posted
117 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Similar $192k
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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Hardware Design Engineer

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The Senior ASIC Hardware Design Engineer joins the NVLink ASIC Design team to develop high-speed chip-to-chip communication and high-performance, low-power GPU and interconnect subsystems. The role involves contributing to the design and development of next-generation NVLink protocol and GPU subsystem logic, including micro-architecture development, documenting specifications, and implementing RTL. Key responsibilities include debugging with verification teams, optimizing for performance and power goals, and delivering synthesis-clean designs for physical implementation. Candidates must possess a degree in Electrical Engineering, Computer Engineering, or Computer Science and have experience with Verilog, SystemVerilog, and scripting languages like Perl or Python. The work focuses on solving complex hardware challenges in digital systems design, VLSI, and high-speed build methodologies to create functional, routable, and physically implementable silicon solutions.

Skills

Verilog SystemVerilog RTL ASIC Design VLSI Python Perl Micro-architecture Logic Design Timing Closure Synthesis Digital Systems Hardware Engineering

What you'll do

  • Design and develop next-generation NVLink protocols and GPU subsystem logic.
  • Contribute to micro-architecture development and document specifications for GPU and interconnect subsystems.
  • Implement and debug RTL designs to ensure functional and performant operation.
  • Optimize logic designs to meet specific performance and power goals.
  • Deliver synthesis and timing clean designs that are routable and physically implementable.
  • Support hardware engineering activities including floor planning, power/clock distribution, and timing closure.
  • Develop custom flows and tools to support various design activities.

What we're looking for

  • A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 5+ years of industry experience.
  • Solid practical understanding of Verilog and/or SystemVerilog.
  • Relevant project experience in micro-architecture and RTL development of complex designs.
  • Exposure to computer architecture and digital systems designs.
  • Strength in scripting languages such as Perl or Python.
  • Background with low-power build methodologies (preferred).
  • Experience with high-speed build methodologies (preferred).

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