Senior ASIC Hardware Design Engineer

Nvidia

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
Westford, MA
Salary
$136,000–$218,500 / yr
Posted
71 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $177k
$126k most similar roles pay here $228k

This role pays less than 54% of similar roles. Most pay $169,875–$215,537 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Hardware Design Engineer

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As a Senior ASIC Hardware Design Engineer on the NVLink ASIC Design team, you will contribute to the development of next-generation NVLink protocol and GPU subsystem logic. You will work with architects, verification engineers, and physical design engineers to deliver functional, performant, and physically implementable designs for high-speed chip-to-chip communication and low-power interconnect subsystems. Your daily responsibilities include micro-architecture development, documenting specifications, RTL implementation, debugging, and optimizing for performance and power goals. You will also support hardware activities like floor planning, timing closure, and developing design tools. The role requires proficiency in Verilog or SystemVerilog, knowledge of VLSI and computer architecture, and skills in scripting languages like Perl or Python. This position focuses on solving complex technical challenges in high-speed, low-power silicon for GPU and interconnect subsystems.

Skills

Verilog SystemVerilog RTL ASIC Design VLSI Python Perl Micro-architecture Digital Systems Timing Closure Logic Design Synthesis floor plan

What you'll do

  • Design and develop next-generation NVLink protocol and GPU subsystem logic.
  • Contribute to micro-architecture development and document specifications for interconnect subsystems.
  • Implement RTL designs and debug them in coordination with the verification team.
  • Optimize logic designs to meet specific performance and power goals.
  • Deliver synthesis and timing clean designs that are physically implementable.
  • Support hardware engineering activities including floor planning, power/clock distribution, and timing closure.
  • Develop custom flows and tools to support various design activities.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 5+ years of industry experience.
  • Solid practical understanding and proficiency in Verilog and/or SystemVerilog.
  • Relevant project experience in micro-architecture and RTL development of complex designs.
  • Exposure to computer architecture and digital systems designs.
  • Proficiency in scripting languages such as Perl or Python.
  • Understanding of physical implementation and VLSI.
  • Experience with low-power and high-speed build methodologies is preferred.

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