Logic Design Engineer

Microsoft

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$102,100–$202,200 / yr
Posted
6 days ago
Freshness
Confirmed live yesterday
Closes
Apr 19, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $152k
$87k $245k
below market most similar roles pay here above market

This role pays less than 86% of similar roles. Most pay $165,625–$229,650 — the blue band above. At the midpoint, this role pays about $152k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

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At a glance

TL;DR · Logic Design Engineer

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The Logic Design Engineer joins the Compute Silicon & Manufacturing Engineering organization within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering. This role focuses on the microarchitecture and logic design of clock controllers for the Azure Cobalt chips. The engineer will develop and integrate functional block RTL for SOC clock controllers while performing design quality checks including Timing closure, Lint, CDC, Synthesis, and Low Power Intent. Key responsibilities involve interfacing with verification and physical design teams, writing basic tests, and using scripting to automate tasks. The position requires proficiency in Verilog and System Verilog, along with knowledge of UPF, timing constraints, and front-end tools like VCLP and Verilog simulators. The work addresses the technical challenge of delivering high-quality, high-volume cloud hardware infrastructure.

Skills

Verilog System Verilog RTL Logic Design Synthesis Timing Closure Lint CDC UPF Low Power Analysis Formal Equivalence Verification Power Analysis ARM Scripting VCLP Verilog Simulators

What you'll do

  • Develop and integrate functional block RTL for SoC clock controllers.
  • Perform design quality checks including timing closure, lint, CDC, synthesis, and low power intent.
  • Interface with verification and physical design teams to deliver qualified physical partitions.
  • Write basic tests and debug features at both the IP and SoC levels.
  • Automate development tasks using scripting to improve process efficiency.
  • Utilize AI tools to increase efficiency within the design and development process.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
  • Must provide proof of citizenship, U.S. permanent residency, or other protected status for export control regulations.
  • Minimum 2+ years of logic design experience (preferred).
  • 2+ years of experience designing clock controller IP (preferred).
  • Proficient in Verilog/System Verilog coding constructs (preferred).
  • Knowledge of logic design flow including Low Power Analysis, UPF, RTL coding, Synthesis, and timing closure (preferred).

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