Senior Hardware Engineer, SoC Electrical Failure Analysis

What you'll do

• Lead and participate in failure analysis efforts to determine contributing factors and corrective actions.
• Drive activities to improve product performance, yield, and reliability.
• Define and refine post-silicon validation plans for functionality, performance characterization, and reliability.
• Capture and interpret device performance metrics including waveforms, eye diagrams, jitter, and BER.
• Validate system-level behavior under real-world networking workloads.
• Contribute to the chip screening test and observability software library using Python and C++.
• Support post-silicon bring-up, manufacturing, and field issue resolution.

What we're looking for

• You must live within commuting distance of the San Jose, CA office and commute 3-5 days per week.
• You must have a Bachelor's degree and 6+ years of experience, a Master's degree and 3+ years of experience, or a PhD and 1+ year of experience.
• You must have relevant experience in electrical post-silicon validation, SoC failure analysis, power and signal integrity, high-speed mixed-signal design, DFT, or SRAM design.
• You must have experience in driving SoC failure analysis efforts.
• You must be able to capture and interpret device performance, waveforms, eye diagrams, jitter, BER, PDN measurements, and power supply stability.
• You must be able to define and refine post-silicon validation plans for functionality, performance characterization, and reliability.
• You should have experience bringing up complex SoCs (preferred).
• You should have experience with electrical diagnostics equipment, high-speed physical interfaces, and software development in Python or C++ (preferred).