Senior Hardware Engineer, SoC Electrical Failure Analysis

Cisco

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$165,000–$241,400 / yr
Posted
52 days ago
Freshness
Confirmed live 2 days ago
Closes
Sep 29, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $203k
$135k most similar roles pay here $253k

This role pays more than 62% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · Senior Hardware Engineer, SoC Electrical Failure Analysis

Senior Hardware Engineer - SoC Electrical Failure Analysis joins the Electrical Post-Silicon Validation Team to ensure the reliability and quality of complex ASICs throughout their lifecycle. This role involves leading failure analysis efforts, improving product yield, and refining post-silicon validation plans for functionality, performance characterization, and reliability. Day-to-day responsibilities include capturing and interpreting device performance metrics such as waveforms, eye diagrams, jitter, BER, and power supply stability while validating system behavior under real-world networking workloads. The candidate will utilize tools like oscilloscopes, VNA, BERT, and logic analyzers to perform electrical diagnostics. Technical requirements include expertise in high-speed mixed-signal design, DFT, and SRAM integration, alongside proficiency in Python and C++ for developing chip screening test and observability software libraries. The work focuses on solving complex hardware challenges within the networking domain for high-performance switching and routing products.

What you'll do

  • Define and refine post-silicon validation plans for functionality, performance characterization, and reliability.
  • Perform electrical post-silicon validation including Vmin, leakage, and PVT characterization.
  • Capture and analyze device metrics such as waveforms, eye diagrams, jitter, BER, and power supply stability.
  • Lead and participate in SoC failure analysis to determine contributing factors and corrective actions.
  • Drive initiatives to improve product performance, manufacturing yield, and overall reliability.
  • Validate system-level behavior under real-world networking workloads.
  • Contribute to the chip screening test and observability software library using Python or C++.

What we're looking for

  • Must hold a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of experience.
  • Must hold a Master's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of experience.
  • Must hold a PhD in Electrical Engineering, Computer Engineering, or a related field with 1+ year of experience.
  • Experience is required in electrical post-silicon validation, SoC failure analysis, and power/signal integrity.
  • Experience is required in high-speed mixed-signal design, DFT, and SRAM design or integration.
  • Proficiency in using electrical diagnostics and measurement equipment such as Oscilloscopes, VNA, BERT, and logic analyzers.
  • Ability to develop software for chip screening tests using Python or C++.
  • Must live within commuting distance of the San Jose, CA office and commute 3-5 days per week.

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