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Python C++ Matlab RF components RF cable bias tee DC block sampling scope real-time scope PPG BERT VNA electrical spectrum analyzer IEEE 802.3 OIF specifications Signal integrity DSP communication systems +13 more Show less

Python Perl C/C++ SystemC AMBA AXI/CHI PCIe ESUN UALink Power Management RTL Design SoC Design Flow Implementation & Verification Computer Architecture Custom ASIC/SoC Projects High-Speed Interface Protocols Design for Debug/Test/Excellence +11 more Show less

AutoCAD SolidWorks PackAssistant MIL specs hazardous material packaging ERP WMS CI/CD Python SQL PostgreSQL AWS Kubernetes +8 more Show less

VHDL Verilog Altium Designer DO-254 DO-178C DO-160 DO-311A MIL-STD-810 MIL-STD-704 MIL-STD-461 +5 more Show less

Python Matlab PCB design switch mode power supply design digital electronics analog electronics troubleshooting documentation scripting languages +4 more Show less

Linux Python Perl TCL Kubernetes Docker CI/CD Prometheus Grafana PostgreSQL AWS Git Jenkins +8 more Show less

FPGA Vivado Digital Signal Processing C C++ Linux DSP Algorithms RTL Development Timing Closure Resource Optimization System-Level Software integration code Epiq Solution PDK +8 more Show less

Ethernet Switches Optical_Interconnects BER_Analysis Link_Stability Signal_Integrity BERT_Analyzers Oscilloscopes Protocol_Analyzers Test_Automation Validation_Frameworks CI/CD Kubernetes AWS Oracle_Cloud +10 more Show less

Mentor_Graphics schematic PCB_layout MathCad PSpice Saber Ethernet PCIe SerDes eFuse FET Thermal LiB DC_DC FMEA Preliminary_Hazard_Analyses embedded_software verification_and_validation high_speed_Communication_Buses Body_controls lighting_controls +16 more Show less

IEC 60601 Electronic PCB design Schematics Circuit simulation PCB Assembly Drawings Design Controls Risk Management Change Control Quality Engineering CI/CD Statistical Analysis Python PostgreSQL Git JIRA Confluence +11 more Show less

C++ Perl Python Make Verilog RTL ASIC Design Clocks/Resets_design_and_verification +3 more Show less

Cadence_APD SiP_tool_suite Constraint_Manager Virtuoso Calibre Valor PCB_layout HDI_design High_speed_design Signal_integrity_practices Python Go Docker CI/CD +9 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux +8 more Show less

Cadence_APD SiP_tool_suite Constraint_Manager Virtuoso Calibre Valor HDI_design PCB_layout Wire_bond_packages Flip_chip_packages +5 more Show less

Mentor_Graphics PCB_layout_design High_speed_Communication_Buses Ethernet PCIe SerDes Design_rule_checks Design_for_Manufacturability ECAD_library_parts Digital_analog_HW_interfaces Mentor_Graphics_schematic_and_layout Simulation_tools Component_engineering Procurement Supply_chain_teams Design_for_Assembly SI_PI_EMC_Thermal_Mechanical_expertise +12 more Show less

Mentor_Graphics_Xpedition Mentor_Graphics_ORCAD PCB_layout Circuit_design Schematic_creation Oscilloscopes Signal_generators Multimeters Power_supplies Automotive_software_architecture Automotive_electronic_hardware Semiconductor_design Electrical_Engineering Electronic_control_unit CI/CD +10 more Show less

Mentor_Graphics Ansys Simplis Altair Mathcad PSpice Saber ISO_26262 ASIL CAN GMLAN LIN OBD-II DFMEA PFMEA Design_for_Manufacturing Design_for_Assembly Design_for_Testing Embedded_Software_Development Controller_Design_Process Vehicle_Dynamics Electrical_Schematic_Design PCB_Layout Signal_Integrity Power_Integrity +20 more Show less

ANSYS_HFSS ANSYS_Q3D ANSYS_SIWAVE PCIe USB_4 GDDR6 LPDDR5X PDN_evaluation layout_extraction_tools spice_based_simulations VNA TDR DSO ParBERT JMP MATLAB +11 more Show less

DFMEA FIT FMEDA FTA Mentor Cadence Medini Plato-e1ns Siemens SN29500 IEC 62380 ISO 26262 IEC 61508 IEC 62304 DO-178C ISO 21448 UL 4600 +11 more Show less

Cadence VLSI ASIC SerDes PLL Analog to Digital converters ESD structures CMOS Sub-micron CMOS technologies +4 more Show less