Principal ASIC Engineer, Reliability & Hardware Validation

Cisco

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $250,600–$362,600 / yr
Employment: Full-time
Posted: 4 days ago
Freshness: Confirmed live yesterday
Closes: Oct 31, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $307k

$123k $388k

below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $168,175–$217,500 — the blue band above. At the midpoint, this role pays about $307k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 261 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 197 roles with salary data.

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At a glance

TL;DR · Principal ASIC Engineer, Reliability & Hardware Validation

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The Principal ASIC Engineer (Reliability & Hardware Validation) joins the Hardware Engineering Team to lead reliability and hardware design validation for next-generation semiconductor and networking products. This role involves defining qualification plans for high-power solutions, executing HTOL, Burn-In, and stress testing, and managing reliability suppliers. The engineer will perform hardware design, schematic generation, and board bring-up for service provider routing products while driving failure analysis. Key technical requirements include expertise in JEDEC, AEC, and Telcordia standards, along with proficiency in Cadence Allegro, Python, Perl, TCL, and Verilog. The position requires deep knowledge of high-speed interfaces, signal integrity, and power distribution for systems exceeding 100Gbps. The work focuses on ensuring product integrity and reliability within hyperscale environments through advanced node packaging and rigorous testing methodologies.

Skills

Semiconductor Reliability High-Speed Design Signal Integrity Power Design Python Perl TCL Verilog Cadence Allegro JMP Reliasoft Minitab FMEA HTOL Burn-In HAST TC HTS ESD LU SER PCIe Gen5/6 800G Ethernet SerDes NRZ PAM4 CoWoS SoIC EMIB JEDEC AEC Telcordia

What you'll do

Define and execute product and process qualification plans for next-generation high-power solutions.
Drive robust HTOL, Burn-In, and stress testing while managing reliability suppliers and subcontractors.
Lead hardware design, schematic generation, and design validation for service provider routing products.
Manage board bring-up and debug processes to ensure hardware functionality.
Drive failure analysis activities and generate detailed qualification reports to ensure product integrity.
Partner with cross-functional teams to support design-for-reliability and high-speed interface compliance.
Provide technical documentation and support for customer quality and reliability requirements.

What we're looking for

Master’s degree in electrical engineering, Computer Engineering, or a related field.
10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
Proven experience in developing high-power HTOL/Burn-In testing for advanced node products.
Deep knowledge of JEDEC, AEC, and Telcordia standards.
Hands-on experience with high-speed network interfaces, board design, and Cadence Allegro.
Experience with high-speed measurement equipment, automated test development, and data analysis/debug.
PhD in Electrical or Computer Engineering (preferred).
Experience with 2nm/3nm Hyperscaler Multi-Chip-Modules and advanced packaging (preferred).

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