Senior FPGA Engineer, Payload Hardware Development

Amazon Inc

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Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$159,200–$215,300 / yr
Posted
68 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $187k
$142k $227k
below market most similar roles pay here above market

This role pays more than 58% of similar roles. Most pay $160,000–$214,625 — the blue band above. At the midpoint, this role pays about $187k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior FPGA Engineer, Payload Hardware Development

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The Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware joins the hardware development team to create FPGA solutions for a low Earth orbit satellite broadband network. This role involves owning FPGA bitstreams through the entire lifecycle, including uArchitecture, RTL Design, Physical Implementation, Timing Closure, Simulation Validation, and Lab Based Silicon Validation. The engineer will design and implement complex digital logic functions for networking functions using Verilog HDL, SystemVerilog, and SystemC. Key responsibilities include developing RTL code for Versal ACAP and IGLOO2 platforms, performing timing analysis, and creating test benches using Vivado, Libero SoC, or ModelSim. The position requires expertise in high-speed interfaces like PCIe, DDR, Ethernet, and SerDes to solve technical challenges in satellite communication systems and hardware integration.

Skills

FPGA Verilog SystemVerilog RTL Design UVM SystemC Vivado Libero SoC ModelSim Versal ACAP IGLOO2 PCIe DDR Ethernet SerDes SPI I2C I3C UART Post-Silicon Validation

What you'll do

  • Design and implement complex FPGA architectures using Verilog HDL for satellite communication systems.
  • Lead FPGA design efforts for Versal ACAP and IGLOO2 platforms from concept through production.
  • Develop and optimize RTL code for high-performance, resource-efficient designs.
  • Perform timing analysis, synthesis, place and route, and design verification.
  • Create comprehensive test benches and simulation environments for digital logic functions.
  • Debug and troubleshoot FPGA designs at both simulation and hardware levels.
  • Drive trade-off analysis to optimize target technology resources for cost, size, power, and performance.
  • Support hardware integration, manufacturing, and production deployment activities.

What we're looking for

  • Must be a U.S. citizen, national, permanent resident, refugee, or granted asylum.
  • Bachelor's degree in Electrical Engineering or a related field with 10+ years of experience.
  • 7+ years of experience with Verilog and/or SystemVerilog HDL for RTL design and verification.
  • 7+ years of experience with FPGA design tools such as Vivado, Libero SoC, or equivalent.
  • 7+ years of experience with simulation tools like ModelSim or Vivado Simulator.
  • 5+ years of experience with UVM using SystemVerilog and/or SystemC.
  • Experience with high-speed interfaces (PCIe, DDR, Ethernet, SerDes) and serial protocols (SPI, I2C, I3C, UART).
  • Export Control Requirement: Due to applicable export control laws and regulations, candidates.

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