Senior FPGA Engineer, Payload Hardware Development

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $159,200–$215,300 / yr
Posted: 22 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $193k

This role $187k

$148k most similar roles pay here $228k

This role pays more than 50% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $193k for comparable roles.

Based on 240 similar postings.

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About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 457 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 447 roles with salary data.

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At a glance

TL;DR · Senior FPGA Engineer, Payload Hardware Development

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As a Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware, you will join the hardware development team to create FPGA solutions for a low Earth orbit satellite communication system. You will own multiple bitstreams, managing the full lifecycle from uArchitecture and RTL design through physical implementation, timing closure, and lab-based silicon validation. Your daily work involves developing digital designs for networking functions using Verilog HDL and SystemVerilog. You will collaborate with system architects and hardware engineers to implement logic on Versal ACAP and IGLOO2 platforms while managing high-speed interfaces like PCIe, DDR, Ethernet, and SerDes. The role requires expertise in Vivado, Libero SoC, and UVM for simulation environments. You will solve complex technical challenges related to signal processing and communications to optimize hardware resources for cost, size, power, and performance within the satellite infrastructure.

Skills

FPGA Verilog SystemVerilog RTL Design UVM Vivado Libero SoC ModelSim Versal ACAP IGLOO2 PCIe DDR Ethernet SerDes SPI I2C I3C UART Timing Analysis Simulation

What you'll do

Design and implement complex FPGA architectures using Verilog HDL for satellite communication systems.
Manage the full lifecycle of FPGA bitstreams from uArchitecture and RTL design to physical implementation and timing closure.
Develop and optimize high-performance, resource-efficient RTL code for Versal ACAP and IGLOO2 platforms.
Create comprehensive test benches and simulation environments to validate digital logic functions.
Perform timing analysis, synthesis, place and route, and hardware-level debugging of FPGA designs.
Conduct trade-off analyses to optimize system performance regarding cost, size, power, and features.
Support hardware integration, manufacturing, and production deployment activities for satellite components.

What we're looking for

Must be a U.S. citizen, national, permanent resident, or lawfully admitted refugee/asylee for export control compliance.
Bachelor's degree in Electrical Engineering or a related field with 10+ years of experience.
Master's or Ph.D. degree in Electrical Engineering or related field (preferred).
7+ years of experience with Verilog and/or SystemVerilog HDL for RTL design and verification.
7+ years of experience with FPGA design tools like Vivado, Libero SoC, or equivalent.
7+ years of experience with simulation tools such as ModelSim or Vivado Simulator.
5+ years of experience with UVM (SystemVerilog and/or SystemC).
Experience with high-speed interfaces (PCIe, DDR, Ethernet, SerDes) and serial protocols (SPI, I2C, I3C, UART).
Experience with Versal ACAP or IGLOO2 platforms, volume production, power gating, or SOC bring-up (preferred).