Senior FPGA Engineer, LEO Payload FPGA

Amazon Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CARedmond, WANorthridge, CA
Salary
$185,200–$250,000 / yr
Posted
124 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $182k
This role $218k
$137k $262k
below market most similar roles pay here above market

This role pays more than 88% of similar roles. Most pay $160,000–$204,125 — the blue band above. At the midpoint, this role pays about $218k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior FPGA Engineer, LEO Payload FPGA

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Senior FPGA Engineer, LEO Payload FPGA The Senior FPGA Engineer, LEO Payload FPGA joins the hardware development team to create FPGA solutions for the LEO low Earth orbit satellite broadband network. This role involves owning FPGA bitstreams through the entire development lifecycle, including uArchitecture, RTL design, physical implementation, timing closure, simulation validation, and lab-based silicon validation. The engineer will collaborate with systems architects to implement digital logic functions and networking functions for satellite communication. Key responsibilities include driving trade-off analyses for cost, size, power, and performance. Required skills include System Verilog, Xilinx/AMD or Altera FPGAs, and Python for test scripts. Candidates should possess experience with high-speed networking, SerDes, 50G/100G Ethernet, Interlaken, and AXI4 or AXI Streaming interfaces to solve complex satellite communication problems.

Skills

FPGA System Verilog RTL Design Python Xilinx AMD Altera Cocotb SerDes Ethernet AXI4 AXI Streaming Simulation Timing Closure ASIC Digital Communications

What you'll do

  • Create and release FPGA bitstreams through uArchitecture, RTL design, physical implementation, and timing closure.
  • Develop digital designs for networking functions using the latest FPGA technologies and tools.
  • Implement digital logic functions in FPGA prototypes to validate and trade off architecture alternatives.
  • Perform simulation validation and lab-based silicon validation for FPGA designs.
  • Bring up and test systems combining FPGA, firmware, RF, and networking functions.
  • Drive trade-off analysis to optimize technology resources for cost, size, power, and performance.
  • Write Python test scripts to validate FPGA images in hardware and Cocotb simulation environments.

What we're looking for

  • Must be a U.S. citizen, national, permanent resident, or lawfully admitted as a refugee or granted asylum.
  • Bachelor's degree in Electrical Engineering or a related field.
  • 7+ years of experience in FPGA design and implementation using SystemVerilog.
  • Experience with modern ASIC/FPGA design and verification tools.
  • Experience with Xilinx/AMD or Altera FPGAs.
  • Experience with uArchitecture, RTL coding, FPGA optimization for timing and power, simulation, and validation.
  • Experience writing test scripts to validate FPGA images in hardware (Python preferred).
  • Export Control Requirement: Due to applicable export control laws and regulations, candidates.

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