Senior FPGA Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: Northridge, CA
Salary: $185,200–$250,000 / yr
Posted: 58 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $175k

This role $218k

$132k $263k

below market most similar roles pay here above market

This role pays more than 93% of similar roles. Most pay $160,000–$190,000 — the blue band above. At the midpoint, this role pays about $218k versus about $175k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior FPGA Engineer

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The Sr. FPGA Engineer joins the Amazon Leo for Government Product Development team to create FPGA solutions for a satellite communication system providing broadband connectivity. You will work with systems and algorithm teams to define, develop, implement, test, and release FPGA-based modem solutions, specifically powering high-speed optical communication links. Daily responsibilities include creating FPGAs through uArchitecture, RTL Design, Physical Implementation, Timing Closure, Simulation Validation, and Lab Based Silicon Validation. You will write RTL code, develop testbenches, and perform debugging in laboratory environments. Required skills include proficiency in Verilog, SystemVerilog, or VHDL; experience with Xilinx Vivado or Microchip Libero; and knowledge of Linux, Python, Perl, PCIe, and DDR. You will also handle trade-off analysis for cost, size, power, and performance within the satellite and ground applications domain.

Skills

FPGA Verilog SystemVerilog VHDL Xilinx Vivado Vitis Microchip Libero Python Perl Linux PCIe DDR SPI I2C I3C UART MATLAB Git CI/CD Agile TDD BDD RTL Design Physical Synthesis

What you'll do

Create and release FPGAs through uArchitecture, RTL Design, Physical Implementation, Timing Closure, and Silicon Validation.
Write RTL code in Verilog, SystemVerilog, or VHDL for high-speed optical communication links.
Develop testbenches and perform simulation and timing closure for modem and digital logic functions.
Debug hardware in a laboratory environment to validate FPGA prototypes and design alternatives.
Perform trade-off analysis to optimize target technology resources for cost, size, power, and performance.
Integrate new and existing IP cores using FPGA design tools like Vivado and Vitis.
Bring up and test systems combining FPGA, firmware, optics, and networking functions.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
Master's degree or Ph.D. degree in Electrical Engineering or related field (preferred).
7+ years of digital design experience in communication systems.
7+ years of verification experience in communication systems.
Proficiency in Verilog, SystemVerilog, or VHDL and experience with Xilinx Vivado or Microchip Libero.
Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems, or RF engineering.
Experience with serial protocols (SPI, I2C, I3C, UART), PCIe, DDR, and Linux scripting (Python/Perl).
Security Clearance: Candidates.

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