Design Verification Engineer

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$102,100–$202,200 / yr
Posted
14 days ago
Freshness
Confirmed live today
Closes
Apr 10, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $152k
$86k $248k
below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $169,625–$230,087 — the blue band above. At the midpoint, this role pays about $152k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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JOB TITLE: Design Verification Engineer The Design Verification Engineer joins the Shared and Custom IP & Silicon team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the design, development, and manufacturing of Microsoft's computer chips, specifically the Azure Cobalt. You will plan verification for complex design IP, identifying test scenarios and creating constrained-random verification environments. Daily responsibilities include developing tests, analyzing failures with designers, and closing functional coverage to meet tape-out requirements. You will utilize SystemVerilog, UVM, SVA, C/C++, and formal verification tools, while potentially using Python, Ruby, or Perl for scripting. The work involves solving hardware manufacturing and quality challenges to optimize cloud infrastructure. You will also engage in chip bring-up activities and write test firmware to ensure functionally correct designs for high-volume production.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

See salary data

Skills

SystemVerilog UVM SVA C C++ Python Ruby Perl Assembly Formal Verification Makefiles SoC Chip Bring-up Firmware Linker Scripts

What you'll do

  • Plan verification for complex design IP by identifying test scenarios with architecture and design engineers.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM.
  • Develop tests using UVM or C/C++ to validate design functionality.
  • Analyze and debug test failures with designers to ensure functionally correct designs.
  • Identify and write functional coverage for stimulus and corner cases.
  • Close coverage to plug verification holes and meet tape-out requirements.
  • Engage in chip bring-up activities and write test firmware to assist other teams.
  • Drive innovation by enhancing validation efficiency through new methodologies and tools.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check.
  • Ability to provide proof of citizenship, US residency, or other protected status for export control assessment.
  • 3+ years of related technical engineering experience or a Doctorate degree in a related field (preferred).
  • Experience executing pre-silicon verification of IPs, Sub Systems, or SoCs through full cycle (preferred).
  • Background in creating and debugging IP/SoC Level tests in SV-UVM/C (preferred).
  • Proficiency in scripting languages such as Python, Ruby, or Perl (preferred).

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