Design Verification Engineer

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$102,100–$202,200 / yr
Posted
11 days ago
Freshness
Confirmed live today
Closes
Apr 13, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $152k
$86k $248k
below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $169,625–$230,087 — the blue band above. At the midpoint, this role pays about $152k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Design Verification Engineer

The Design Verification Engineer joins the Compute Silicon & Manufacturing Engineering team to support the development of custom silicon components for cloud hardware infrastructure. In this role, you will be an integral member of the pre-silicon verification and post-silicon validation teams. Your daily responsibilities include writing constrained random stimulus, scoreboards, checkers, and assertions to ensure design correctness. You will develop Verification IP components and Universal Verification Methodology components to interface test code with simulation environments. Key tasks involve defining functional coverage, driving coverage closure, and developing scripts for verification infrastructure. You will utilize SystemVerilog, C/C++, and scripting languages like Python, Ruby, or Perl. The work focuses on verifying complex IP blocks such as Coherency, Caches, Fabrics, DDR controllers, PCIe, CXL, and AXI/CHI protocol bridges.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

See salary data

What you'll do

  • Write constrained random stimulus, scoreboards, checkers, and assertions to verify design correctness.
  • Develop Verification IP (VIP) components to verify home-grown designs.
  • Develop Universal Verification Methodology (UVM) components to interface test code with simulation environments.
  • Define and implement functional coverage and drive coverage closure.
  • Develop scripts for verification and validation infrastructure.
  • Ensure comprehensive pre- and post-silicon testing through cross-functional collaboration.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check.
  • Ability to provide proof of citizenship, US residency, or other protected status for export control eligibility.
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of technical engineering experience (preferred).
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of technical engineering experience (preferred).
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of technical engineering experience (preferred).
  • 3+ years of experience in SystemVerilog, C/C++, and scripting languages such as Python, Ruby, or Perl (preferred).

More like this

Similar roles

Design Verification Engineer

Amd

Santa Clara, CA 146 days ago $166,400–$249,600
SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

Design Verification Engineer

Microsoft

14 days ago $102,100–$202,200
SystemVerilog UVM SVA C C++ Python Ruby Perl Assembly Formal Verification Makefiles SoC Chip Bring-up Firmware Linker Scripts
2+ yrs exp Hybrid

Principal Design Verification Engineer

Microsoft

13 days ago $142,800–$274,800
SystemVerilog UVM C++ Python Verilog VHDL Ruby Perl Agile Hardware Emulation FPGA Makefiles Scripting Post-Silicon Validation Pre-Silicon Functional Verification
8+ yrs exp Hybrid

Design Verification Engineer

Apple Inc

Austin, TX 136 days ago
UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA LLM ML 4G 5G 3GPP AXI AHB NOC Bus Fabric RTL Simulation

Design Verification Engineer

Apple Inc

Austin, TX 136 days ago
UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA Constraint Random Testing LLM ML RTL Simulation AXI AHB NoC 3GPP 4G 5G
10+ yrs exp

Design Verification Engineer

Broadcom

San Jose, CA 130 days ago $143,800–$230,000
System Verilog UVM OVM C++ SystemC Perl ASIC Design Verification RTL Verification FPGA Emulators Coverage Assertions C Scripting
10+ yrs exp