This role pays less than
62%
of similar roles. Most pay
$174,206–$222,250
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$198k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
518 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 505 roles with salary data.
The Senior Design Verification Engineer joins the AI Silicon Engineering SoC Design Verification team to verify Microsoft’s latest AI accelerators. Working with cross-discipline teams including systems, firmware, and architecture, the engineer develops complex verification environments, test cases, and reference models for pre-silicon functional verification at the block, chip, and system levels. Daily responsibilities include creating test plans, developing components like scoreboards, sequences, constraints, assertions, and functional coverage, while triaging and debugging testbench, simulation, and emulation fails. The role requires proficiency in SystemVerilog, UVM, Verilog, VHDL, C/C++, and scripting languages such as Python, Ruby, or Perl. Additionally, the engineer will develop Makefiles and scripts for scalable verification while utilizing Agile methodologies to solve complex quality and design challenges within the specialized domain of silicon IP and computer architecture.
What does a Design Verification Engineer earn?
Median $195800 from 64 postings across 10 companies.
Create complex verification environments and test cases for block, chip, and system levels.
Develop verification plans covering strategy, test environments, and requirements for IP/SS/SOC levels.
Drive test-plan development to ensure complete feature coverage across the product.
Build verification components including scoreboards, sequences, constraints, assertions, and functional coverage.
Triage and debug failures in testbenches, simulations, and emulations.
Develop Makefiles and scripts to ensure scalable and efficient verification processes.
Solve complex technical challenges related to quality and design.
What we're looking for
A PhD in Electrical Engineering, Computer Engineering, or Computer Science and 1+ years of experience, OR a Master's and 4+ years, OR a Bachelor's and 5+ years.
Ability to pass Microsoft Cloud Background Check and meet export control regulations regarding citizenship or residency status.
Experience creating simulation environments, developing tests, and debugging for multiple silicon IPs or systems (preferred).
At least 1 year of industry experience in chip or computer architecture (preferred).
At least 1 year of industry experience in Verilog, VHDL, C/C++, and scripting languages like Python, Ruby, or Perl (preferred).
Experience with CPU or graphics core verification, SystemVerilog, UVM, and hardware emulation or FPGAs (preferred).
Experience in firmware development, hardware design for embedded systems, or writing synthesizable code (preferred).
Effective communication skills and a self-motivated attitude (preferred).
UVM
SystemVerilog
Verilog
Python
C++
HLS
VCS
Verdi
GDB
DisplayPort
HDMI
MIPI DSI
Assertion-based Verification
Functional Coverage
Constrained-random
Version Control