This role pays less than
62%
of similar roles. Most pay
$176,493–$224,075
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$200k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
518 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 505 roles with salary data.
The Senior Design Verification Engineer joins the Shared & Custom IP and Silicon Security team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the verification of complex design IP for cloud infrastructure hardware. You will plan verification strategies with architecture and design engineers, create and enhance constrained-random environments using SystemVerilog and UVM, or perform formal verification using SVA and industry-leading tools. Daily responsibilities include developing tests in UVM or C/C++, analyzing test failures, writing functional coverage for corner cases, and participating in chip bring-up activities by writing test firmware. The role requires proficiency in SystemVerilog, UVM, C/C++, and scripting languages like Python, Ruby, or Perl. You will solve critical hardware manufacturing and quality challenges to ensure the reliable delivery of high-volume cloud infrastructure components for large-scale data center operations.
What does a Design Verification Engineer earn?
Median $195800 from 64 postings across 10 companies.
Plan verification for complex design IPs by identifying test scenarios with architecture and design engineers.
Create and enhance constrained-random verification environments using SystemVerilog and UVM.
Perform formal verification of designs using SVA and industry-leading formal tools.
Develop functional tests using UVM or C/C++.
Analyze and debug test failures to ensure the delivery of functionally correct designs.
Define and write functional coverage for stimulus and corner cases to meet tape-out requirements.
Participate in chip bring-up activities and write test firmware to support other teams.
Improve validation efficiency by developing new verification methodologies and tools.
What we're looking for
A Doctorate with 1+ years experience, a Master's with 4+ years experience, or a Bachelor's with 5+ years of technical engineering experience is required.
Candidates must be able to pass the Microsoft Cloud Background Check and meet export control regulations.
Candidates must provide proof of citizenship, residency, or other protected status for export control assessment.
Experience in executing pre-silicon verification of IPs, Sub Systems, or SoCs through a full cycle (preferred).
Background in creating and debugging IP/SoC level tests in SV-UVM/C (preferred).
In-depth knowledge of verification principles, testbenches, and stimulus generation (preferred).
Proficiency in scripting languages such as Python, Ruby, or Perl (preferred).
Experience with formal verification methods, AI tools for productivity, and leading designs from architecture to freeze (preferred).
UVM
SystemVerilog
Verilog
Python
C++
HLS
VCS
Verdi
GDB
DisplayPort
HDMI
MIPI DSI
Assertion-based Verification
Functional Coverage
Constrained-random
Version Control