Design Verification Engineer

Microsoft

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$102,100–$202,200 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Closes
Mar 15, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $203k
This role $152k
$86k most similar roles pay here $251k

This role pays less than 92% of similar roles. Most pay $177,250–$229,100 — the shaded band above. At the midpoint, this role pays about $152k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 518 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 505 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Design Verification Engineer

The Design Verification Engineer joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization to support cloud infrastructure hardware. In this role, you will own the verification of components used in Fabric Interconnect by collaborating with partner teams to define strategies and test plans. You will develop UVM-based or Formal verification environments, run and debug simulations, and apply random-stimulus and coverage-based techniques to identify bugs. The position involves innovating verification efficiency through new methodologies, tools, and generative AI solutions while mentoring others in your area of expertise. Key technical requirements include proficiency in System Verilog Test Bench, Python for post-processing, and experience with CHI and AMBA protocols. You will address critical hardware challenges involving fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and protocol bridges to ensure high-quality cloud hardware manufacturing.

What does a Design Verification Engineer earn?

Median $195800 from 64 postings across 10 companies.

See salary data

What you'll do

  • Own the verification of components used in Fabric Interconnect.
  • Define verification strategies and test plans in collaboration with partner teams.
  • Develop UVM-based or Formal verification environments to drive product quality.
  • Run and debug simulations using random-stimulus and coverage-based techniques.
  • Innovate new methodologies and tools to improve verification efficiency.
  • Integrate generative AI solutions into daily verification workflows.
  • Coach and mentor team members in specific areas of expertise.

What we're looking for

  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of experience, or Bachelor's with 2+ years.
  • Ability to pass Microsoft Cloud Background Check and meet export control regulations.
  • Proof of citizenship, residency, or other protected status is required for export-controlled information access.
  • Doctorate degree, or Master's with 3+ years experience, or Bachelor's with 5+ years experience (preferred).
  • Demonstrated understanding of designs utilizing Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols (preferred).
  • Understanding of fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges (preferred).
  • Experience with IP verification from definition to silicon, including test plans, debugging, and coverage signoff (preferred).
  • Experience with UVM, SystemVerilog, Python, or applying generative AI to daily tasks (preferred).

More like this

Similar roles

Formal Design Verification Engineer

Microsoft

57 days ago $119,800–$234,700
Formal Verification UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI SVTB Silicon Engineering Verification Methodology
5+ yrs exp

Design Verification Engineer II

Microsoft

15 days ago $102,100–$202,200
UVM System Verilog Formal Verification Python PCIe CXL AXI AMBA CHI Generative AI Simulations Coverage Signoff
2+ yrs exp Hybrid

Design Verification Engineer

Apple Inc

Austin, TX 111 days ago
UVM System Verilog Python C++ SVA coverage driven verification LLM RTL Simulation 3GPP AXI AHB NoC Perl Constraint Random Testing Firmware

Design Verification Engineer

Broadcom

San Jose, CA 105 days ago $143,800–$230,000
System Verilog UVM OVM C C++ SystemC Perl RTL Verification ASIC Design FPGA Emulators DSP Scripting
10+ yrs exp

Design Verification Engineer

Broadcom

San Jose, CA 105 days ago $143,800–$230,000
System Verilog UVM OVM C C++ Perl SystemC RTL Verification ASIC Design FPGA Emulators DSP Scripting