Cell Modeling and Verification Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $100,000–$166,750 / yr
Employment: Full-time
Posted: 63 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k

This role $133k

$85k $236k

below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $152,875–$216,250 — the blue band above. At the midpoint, this role pays about $133k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Cell Modeling and Verification Engineer

Role Posting Log in to save

JOB TITLE: Cell Modeling and Verification Engineer - New College Grad 2026 The NVIDIA VLSI team is seeking a Cell Modeling and Verification Engineer - New College Grad 2026 to develop groundbreaking ASIC products. In this role, you will work at the intersection of circuit and digital design to craft power-efficient, performance-leading SoCs and GPUs. Your daily responsibilities include developing behavioral models and verification for custom mixed-signal design cells used across all products. You will model, verify, emulate, and prototype mixed-signal designs while collaborating with cross-functional teams on library builds, cell integration, ASIC verification, and DFT simulation. You must utilize Verilog, SystemVerilog, Perl, and Python to deliver fully verified RTL. The position requires a strong understanding of PLLs, high-speed interconnects, fundamental digital design, logic design concepts, and hands-on experience with RTL simulation and waveform debug.

Skills

Verilog SystemVerilog Python Perl RTL ASIC Verification DFT Mixed-Signal Design Digital Design Logic Design Waveform Debug PLL High-Speed Interconnects Simulation Hardware Design

What you'll do

Develop behavioral models and verification for custom mixed-signal design cells.
Use Verilog, SystemVerilog, Perl, or Python to model and verify mixed-signal designs.
Model and verify high-speed interconnects and PLLs for ASIC products.
Document, implement, and deliver fully verified high-performance RTL to meet design targets.
Perform RTL simulation and waveform debugging for hardware designs.
Coordinate with cross-functional teams on library builds, cell integration, and DFT simulation.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
Hands-on experience with RTL simulation and waveform debug.
Strong understanding of Verilog HDL.
Scripting experience and skills using Python or Perl.
Knowledge of fundamental digital design and logic design concepts.
Previous digital design experience (preferred).
Previous experience running simulations in Verilog (preferred).
Ability to collaborate with many groups and communicate technical details (preferred).

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