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Senior ASIC Timing Engineer

Nvidia

Santa Clara, CA 3 days ago $136,000–$218,500
Actively hiring Posted this week Verified listing Competitive pay
Static Timing Analysis Timing Constraints Generation ECOs Physical Design Optimization Synthesis Placement Routing Logic Restructuring STA Tools Deep Sub-Micron Process Nodes GPU STA CPU STA LPD STA SOC STA Logic Synthesis Equivalence Checking DFT Logic AMS Designs Methodology Development Flow Development Automation
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Senior ASIC Timing Engineer

Nvidia

Westford, MA 8 days ago $168,000–$264,500
Actively hiring Verified listing Above market
Python Tcl Make Synopsys_PrimeTime Cadence_Tempus EDA_tools Static_Timing_Analysis Timing_Constraints_Generation ECOs Physical_Design_Optimization Logic_Synthesis Logical_Equivalence_Checking DFT_logic Deep_Sub_Micron_Technology Process_Variations_Modeling Methodology_Development_Automation
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