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ASIC Design Engineer, Clocks IP

Nvidia

Santa Clara, CA +1 8 days ago $116,000–$189,750
Actively hiring Confirmed live yesterday High trust Below market
RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV Effects SOC Verification
2+ yrs exp Hybrid
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ASIC Clocks Verification Engineer

Nvidia

Santa Clara, CA 18 days ago $116,000–$189,750
Actively hiring Confirmed live today High trust Below market
SystemVerilog UVM Python Perl Logic Design Logic Synthesis Design Verification DFT Clocking Structures Scripting
Hybrid
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Senior ASIC Design Engineer, Clocks IP

Nvidia

Santa Clara, CA +1 21 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification
3+ yrs exp Hybrid
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