Processor ASIC RTL Design Engineer

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$127,200–$190,800 / yr
Posted
126 days ago
Freshness
Confirmed live 2 days ago
Closes
Nov 4, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $159k
$114k most similar roles pay here $248k

This role pays less than 85% of similar roles. Most pay $175,000–$223,000 — the shaded band above. At the midpoint, this role pays about $159k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Processor ASIC RTL Design Engineer

Role Posting Log in to save

The Processor ASIC RTL Design Engineer joins the DSP Architecture and Design team to develop high-performance, low-power Hexagon and NPU cores for mobile SoC, Server IoT, and Automotive applications. This role involves defining micro-architecture documentation with system teams, developing RTL for multiple logic blocks, and performing area and power optimizations. The engineer will manage frontend tools for linting, clock domain crossing, and power intent while collaborating with physical design and verification teams on timing closure and test plans. Key technical requirements include proficiency in SystemVerilog, Verilog, and digital design, alongside experience with bus interfaces, cache, and computer architecture. The role addresses the challenge of designing complex processor integrations within advanced technology flows, ensuring robust integration for diverse applications including AI, audio, and modem technologies through rigorous RTL development and hardware integration support.

Skills

RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis

What you'll do

  • Define micro-architecture documentation for Hexagon/NPU blocks and sub-systems with the architecture team.
  • Develop RTL for multiple logic blocks of Hexagon/NPU and sub-systems for SoC integration.
  • Execute frontend tools to verify linting, clock domain crossing, and power intent.
  • Coordinate with physical design teams to manage design constraints and achieve timing closure.
  • Perform area and power optimization for integrated circuits.
  • Collaborate with verification teams on test plans, debug processes, and coverage closure.
  • Support internal hardware integration across the SoC platform.
  • Propose innovations for ASICs, IP cores, and manufacturing process flows.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • 2+ years of experience with high-performance microprocessor design.
  • 2+ years of practical experience with functional and structural RTL design in SystemVerilog.
  • Experience with advanced tools for linting, clock domain crossing (CDC), logic equivalence check (LEC), and constraint programming (CLP).
  • Knowledge of ASIC design flow from RTL to GDS2 including synthesis, static timing analysis, and low power techniques.
  • Familiarity with processor integration, bus interfaces, and computer architecture is highly desirable.

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