RISCV CPU System RTL Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CASan Diego, CAAustin, TXRaleigh, NC
Salary
$147,900–$221,900 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k
This role $185k
$135k $273k
below market most similar roles pay here above market

This role pays less than 64% of similar roles. Most pay $172,000–$231,150 — the blue band above. At the midpoint, this role pays about $185k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · RISCV CPU System RTL Engineer

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The RISCV CPU System RTL Engineer joins the CPU Engineering team to develop RISCV CPU RTL for high-performance, low-power devices. The engineer will contribute to architecture and product definition while owning the microarchitecture and RTL execution of CPU system features. Key responsibilities include developing configuration access protocols, timer and interrupt architectures, power management, and debug and trace mechanisms. The role involves exploring performance and power optimization opportunities, creating high-level specifications, and refining RTL to meet power, performance, area, and timing goals. Candidates must possess expertise in RISCV CPU system features, logic design principles, and power management for high-performance systems. Required technical skills include proficiency in Verilog and/or VHDL, experience with simulators and waveform debugging tools, and knowledge of scripting languages like Perl or Python.

Skills

RISCV Verilog VHDL RTL Design Microarchitecture Logic Design Python Perl Power Management Waveform Debugging Simulators Hardware Engineering ISA Scan-dump Memory Dump

What you'll do

  • Develop high-level architecture and microarchitecture specifications for RISC-V CPU system features.
  • Write and refine RTL code to meet specific power, performance, area, and timing goals.
  • Explore performance and power optimization opportunities in coordination with the CPU modeling team.
  • Support the design verification team by executing and assisting with verification strategies.
  • Validate physical design aspects including timing, area, reliability, testability, and power with cross-functional teams.
  • Enable CPU system features by working closely with software, firmware, and platform teams.
  • Implement power management strategies for active and idle states, including limit and clock architecture.

What we're looking for

  • Master’s degree in computer or electrical engineering with 1-3 years of experience in CPU RTL or a related field.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Deep knowledge of microprocessor architecture, including RISCV CPU system features, power management, and debug/trace architecture.
  • Strong expertise in power management for high-performance systems, including active power, idle low power, and silicon/system limits.
  • Proven experience in defining and developing debug features for high-performance designs.
  • Proficiency in Verilog and/or VHDL, and experience with simulators and waveform debugging tools.
  • Experience with scripting languages such as Perl or Python (preferred).

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