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Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 126 days ago $127,200–$190,800
Actively hiring Confirmed live 2 days ago Trusted Below market
RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis
2+ yrs exp
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