Processor Micro Architect RTL Design Engineer

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$180,400–$270,600 / yr
Posted
87 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 13, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $226k
$146k most similar roles pay here $284k

This role pays more than 77% of similar roles. Most pay $175,000–$221,050 — the shaded band above. At the midpoint, this role pays about $226k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Processor Micro Architect RTL Design Engineer

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The Processor Micro Architect RTL Design Engineer joins the DSP Architecture and Design team to develop high-performance, low-power Hexagon cores for mobile SoC, IoT, and automotive applications. This role involves defining micro-architecture for various blocks of the Hexagon DSP core and sub-system while developing RTL for multiple logic blocks intended for SoC integration. The engineer will perform linting, manage clock domain crossing, collaborate with physical design teams on timing closure, and work with low power teams on optimization. Key responsibilities include collaborating with verification teams on test plans and coverage closure. Candidates should possess expertise in Verilog, SystemVerilog, and logic design. Technical requirements include experience with cache, memory coherency, bus protocols, and multi-core microprocessor architecture to solve complex challenges related to advanced technology ASIC design flows from RTL to GDS2.

Skills

RTL Verilog System Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Low Power Design Microprocessor Architecture Cache Bus Protocol Linting Clock Domain Crossing GDS2 Synthesis Simulation Regression

What you'll do

  • Define micro-architecture for various blocks of the Hexagon DSP core and sub-systems.
  • Develop RTL for multiple logic blocks to ensure successful SoC integration.
  • Execute frontend tools to check for linting issues and clock domain crossings.
  • Coordinate with physical design teams to achieve design constraints and timing closure.
  • Implement power optimization techniques in collaboration with the low power team.
  • Collaborate with verification teams to develop test plans and achieve coverage closure.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 2+ years of experience.
  • Master's degree in Electrical Engineering, Computer Engineering, or a related field with 1+ year of experience.
  • PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Bachelor's degree and 6+ years of experience in Software, Electrical, or Systems Engineering.
  • Master's degree and 5+ years of experience in Software, Electrical, or Systems Engineering.
  • PhD and 4+ years of experience in Software, Electrical, or Systems Engineering.
  • At least 2 years of experience with high-performance microprocessor design.
  • Proficiency in RTL design, synthesis, static timing analysis, and low power techniques.

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