Processor ASIC RTL Design Engineer
Qualcomm
At a glance
AI generatedAs a senior RTL design engineer on Qualcomm’s Hexagon team, you will play a crucial role in defining and developing the micro-architecture for various blocks of the Hexagon DSP core and subsystems used in mobile SOCs, IoT devices, and automotive applications. Your daily tasks will include collaborating with architecture teams to define micro-architectures, writing RTL code for integration into SoCs, running linting tools, and working closely with physical design and low power teams on timing closure and optimization. You will also collaborate with verification teams to ensure comprehensive test coverage. Ideal candidates have a strong background in RTL development, including experience with Verilog, SystemVerilog, and digital logic design, as well as knowledge of cache coherency, multi-core microprocessor architecture, and low-power techniques.
Skills
What you'll do
What we're looking for
Market check
This $180,400–$270,600 range sits above 78% of similar postings on FindRole.
Peer median band
$152,000–$231,250
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$160,000–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 564 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 531 roles with salary data.
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