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Active Keyword: Principal Design Verification Engineer Remove filter Clear all

7 of up to 20 (filtered)

Principal Design Verification Engineer, Formal

Microsoft

4 days ago $142,800–$274,800
Actively hiring Confirmed live today Posted this week Trusted Competitive pay
Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools
8+ yrs exp Hybrid
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Principal Design Verification Engineer

Microsoft

14 days ago $142,800–$274,800
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM C++ Python Verilog VHDL Ruby Perl Agile Hardware Emulation FPGA Makefiles Scripting Post-Silicon Validation Pre-Silicon Functional Verification
8+ yrs exp Hybrid
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Principal Design Verification Engineer

SpaceX

Palo Alto, CA +4 159 days ago $210,000–$355,000
Actively hiring Confirmed live today Low trust Above market
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Principal Design Verification Engineer

SpaceX

Irvine, CA +3 159 days ago $210,000–$335,000
Actively hiring Confirmed live today Low trust Above market
ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Principal Design Verification Engineer

SpaceX

Redmond, WA +3 159 days ago $210,000–$335,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Principal Design Verification Engineer

SpaceX

Austin, TX +3 159 days ago
Actively hiring Confirmed live today Low trust
ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design
10+ yrs exp
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Principal Quantum Design Verification Engineer

Microsoft

167 days ago $142,800–$274,800
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog UVM OVM Python C C++ MATLAB Ruby Perl AMS RTL DFT SoC Azure Simulation Validation Characterization
8+ yrs exp Hybrid
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