Principal Design Verification Engineer

What you'll do

• Lead a pre-silicon verification team for the development of custom IP components.
• Create testplans covering verification strategy, test requirements, and test environments for IP verification.
• Write, execute, and debug constrained random stimulus, scoreboards, checkers, and assertions.
• Develop Universal Verification Methodology (UVM) components to interface test code with simulation environments.
• Define and implement functional coverage to drive coverage closure.
• Triage and debug testbench, simulation, and emulation failures.
• Write makefiles and scripts for verification infrastructure.

What we're looking for

• Obtain a Doctorate with 3+ years of experience, a Master's with 6+ years, or a Bachelor's with 8+ years in a relevant engineering field.
• Ability to pass the Microsoft Cloud Background Check.
• Must provide proof of U.S. citizenship, permanent residency, or other protected status for export control eligibility.
• 12+ years of experience in design verification (preferred).
• Experience with verification for multiple product cycles from definition to Silicon using C++ and UVM (preferred).
• Experience debugging RTL designs as well as simulation and/or emulation environments (preferred).
• 5+ years of experience in lead roles across cross-functional and cross-time-zone engineering teams (preferred).
• Verification lead experience for IP or SS related to CPUs, VPUs, GPUs, DMA, Tensor units, or similar (preferred).