Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $165,800–$292,400 / yr
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $229k

$133k $309k

below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $169,625–$241,750 — the blue band above. At the midpoint, this role pays about $229k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3546 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2746 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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JOB TITLE: Design Verification Engineer The Design Verification Engineer joins a hardware group to ensure bug-free first silicon for SoC and IP designs. This role involves all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. The engineer will develop stimulus, checkers, assertions, and trackers while executing design bring-up, regression enabling, and debugging test failures. Key responsibilities include tracking progress through bugs and coverage metrics to achieve sign-off for RTL freeze and tape-out. Required technical skills include SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL. The role also utilizes LLMs for efficient execution and quality. Candidates should possess experience with simulators, waveform viewers, coverage collection, gate level simulations, and power-aware UPF methodologies.

What does a Design Verification Engineer earn?

Median $191650 from 84 postings across 9 companies.

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Skills

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP

What you'll do

Create comprehensive test plans based on design specifications and micro-architecture.
Develop scalable and portable verification environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, and trackers.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using bugs and coverage metrics.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Manage all phases of pre-silicon verification for RTL freeze and tape-out.

What we're looking for

BS degree in a technical subject area.
Minimum 10 years of relevant industry experience or equivalent.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, and coverage collection (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).