Principal Design Verification Engineer

Microsoft

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Salary
$142,800–$274,800 / yr
Posted
21 days ago
Freshness
Confirmed live yesterday
Closes
Feb 17, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 68% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Principal Design Verification Engineer

The Principal Design Verification Engineer joins the AI Silicon Engineering SoC Design Verification team to support the development of advanced AI accelerators. In this role, you will create complex verification environments and test cases for block, chip, and system levels while collaborating with architects and design engineers to establish comprehensive verification plans. Your daily responsibilities include developing components like scoreboards, sequences, constraints, assertions, and functional coverage, as well as triaging and debugging failures in simulation and emulation. You will utilize UVM, SystemVerilog, C++, and Makefiles to build scalable solutions while adopting agentic DV workflows like Co-Pilot. The role requires expertise in pre-silicon functional verification and post-silicon validation within the context of high-performance silicon IP and SoC design. You will also manage test development for full feature coverage using Agile methodologies and cross-functional collaboration.

What you'll do

  • Create complex verification environments and tests using UVM, SystemVerilog, and C++.
  • Develop verification plans for IP, sub-system, and SoC levels in coordination with architects.
  • Drive test development to ensure complete feature coverage across all hardware components.
  • Implement agentic DV workflows and AI methodologies like Co-Pilot into the verification process.
  • Build verification components including scoreboards, sequences, constraints, assertions, and functional coverage.
  • Triage and debug failures across testbenches, simulations, and emulation environments.
  • Develop Makefiles and scripts to ensure scalable and efficient verification processes.

What we're looking for

  • A Doctorate in Electrical Engineering, Computer Engineering, or Computer Science and 3+ years of technical engineering experience.
  • A Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science and 6+ years of technical engineering experience.
  • A Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science and 8+ years of technical engineering experience.
  • Equivalent experience to the specified degree and experience combinations.
  • Ability to pass Microsoft Cloud background checks and meet export control regulations regarding citizenship or residency.
  • Experience creating simulation environments, developing tests, and debugging for multiple silicon IPs or systems (preferred).
  • 5+ years of industry experience in chip/computer architecture, Verilog/VHDL, C/C++, and scripting languages like Python, Ruby, or Perl (preferred).
  • Knowledge of UVM, SystemVerilog, hardware emulation, FPGAs, and advanced verification principles (preferred).

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