This role pays less than
52%
of similar roles. Most pay
$169,625–$216,250
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$193k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
598 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 586 roles with salary data.
The Senior Silicon Design Verification Engineer joins the Shared and Custom IP & Silicon team to support the design, development, and manufacturing of advanced computer chips for cloud infrastructure. This role involves developing C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels. The engineer will serve as a technical owner for FPGA prototyping platforms like HAPS or Xilinx, creating board images and bit files while designing custom RTL for protocol interfaces. Key responsibilities include building Python tooling, performing post-silicon bring-up in lab environments, and debugging issues using JTAG debuggers, logic analyzers, oscilloscopes, and multimeters. The role addresses the technical challenge of ensuring high-quality, scalable hardware production by validating complex designs through pre-silicon verification cycles and resolving critical boot, connectivity, and firmware-related failures to ensure reliable cloud infrastructure performance.
Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels.
Extend compile and build flows to support custom firmware-style tests.
Serve as technical owner for FPGA prototyping platforms by creating board images, bit files, and custom RTL.
Develop and extend custom Python tooling to interface with FPGA platforms.
Debug FPGA and post-silicon issues using JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
Lead post-silicon bring-up and validation in the lab to meet schedule requirements and resolve boot failures.
Root-cause failing post-silicon tests by analyzing scan dumps and coordinating cross-team fixes for low-level bugs.
What we're looking for
A Doctorate in Electrical Engineering, Computer Science, or related field and 1+ year of experience, OR a Master's and 4+ years, OR a Bachelor's and 5+ years.
A Doctorate with 3+ years experience, OR a Master's with 6+ years, OR a Bachelor's with 8+ years (preferred).
Experience developing C/C++ test content for subsystem and SoC verification including bare-metal and firmware-style tests with SystemVerilog knowledge (preferred).
Experience bringing up and maintaining FPGA prototyping or emulation platforms like HAPS or Xilinx (preferred).
Hands-on hardware debug experience using JTAG debuggers, logic analyzers, oscilloscopes, and multimeters (preferred).
Experience owning pre-silicon verification of IP, subsystems, or SoCs through the full cycle (preferred).
Experience with post-silicon bring-up, validation, and debugging boot/platform issues in a lab environment (preferred).
Proficiency in Python or other scripting languages for test automation and build flows (preferred).
Experience with low-level embedded software including assembly, startup code, linker scripts, and Makefile builds (preferred).
Familiarity with industry protocols such as AMBA, JTAG, SPI, I2C/I3C, and USB (preferred).
Ability to pass Microsoft Cloud Background Check and meet export control regulations.