Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 148 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $242k

$115k most similar roles pay here $329k

This role pays more than 88% of similar roles. Most pay $159,750–$216,062 — the shaded band above. At the midpoint, this role pays about $242k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

As a Design Verification Engineer, you will join the silicon design group to ensure the quality and reliability of next-generation cellular systems. You will be responsible for verifying high-throughput cellular baseband modems and transceiver link controllers for System on Chips. Your daily work involves constructing detailed test plans, creating coverage-driven verification plans from specifications, and architecting reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models. To achieve these goals, you will utilize SystemVerilog, UVM, SystemC, C/C++, Python, Perl, SVA, and constraint random testing. You will also implement ML-driven workflows and leverage Large Language Models to enhance verification efficiency. The role focuses on solving complex challenges in cellular protocols, advanced fabric protocols, and low-power architectures while ensuring tape-out readiness for sophisticated IP and subsystem designs within the mobile communication space.

Skills

UVM System Verilog Python C++ System C SVA coverage driven verification LLM RTL Simulation 3GPP AXI AHB NoC Bus Fabric Perl Prompt Engineering

What you'll do

Construct detailed test plans including use cases and coverage goals from technical specifications.
Architect reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models.
Develop coverage-driven verification plans and refine them to meet specific target metrics.
Implement test plans from RTL simulation bring-up through final sign-off while debugging failures.
Integrate Large Language Models (LLMs) and ML-driven workflows to improve verification efficiency.
Maintain regression suites and report progress against test plans and coverage metrics.
Develop Python-based automation solutions to enhance the overall verification process.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Master of Science degree in Electrical Engineering or Computer Science is preferred.
Strong knowledge of SystemVerilog and UVM methodologies.
Proficiency in SystemC, C/C++, Python, and Perl.
Experience with constraint random testing, SVA, and coverage-driven verification.
Experience using LLMs and MCPs to improve verification efficiency and quality.
Experience developing Python-based automation solutions.
Knowledge of 4G/5G cellular physical layer operation (3GPP) is preferred.

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