Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $171,600–$302,200 / yr
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k

This role $237k

$116k most similar roles pay here $322k

This role pays more than 87% of similar roles. Most pay $158,762–$209,750 — the shaded band above. At the midpoint, this role pays about $237k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer at the senior level within our silicon design group, you will play a pivotal role in verifying innovative high-throughput cellular baseband modems and RF link controllers for Apple's SOCs. Your daily responsibilities include crafting comprehensive UVM verification environments, developing coverage-driven test cases, and collaborating with multi-functional teams to ensure tape-out readiness. You will leverage Large Language Models (LLMs) and machine learning techniques to enhance verification processes, improve efficiency, and maintain regressions while reporting progress against coverage metrics. The ideal candidate has hands-on experience in ASIC design verification using UVM methodologies, proficiency in System Verilog, C/C++, Python, and Perl, and a deep understanding of cellular protocols such as 4G/5G physical layer operations (3GPP). This role offers the opportunity to work on cutting-edge technology that impacts millions of users globally.

Skills

SystemVerilog UVM Python Perl LLMs MCPs C C++ SVA Coverage-driven verification RTL simulation Constraint random testing AHB AXI NOC Bus Fabric

What you'll do

Construct detailed test plans for design components through collaboration with multi-functional teams.
Create coverage-driven verification plans from specifications, refining them to meet coverage targets.
Architect UVM-based, reusable test benches including stimulus, checkers, VIPs, and reference models.
Leverage Large Language Models (LLMs) to enhance verification processes, improving efficiency and quality.
Design and implement ML-driven workflows to increase team productivity and overall verification quality.
Implement test plans from RTL simulation bring-up to sign-off, reporting and debugging failures throughout.

What we're looking for

Strong knowledge of System Verilog and Universal Verification Methodology (UVM).
Proficient in developing detailed test plans and coverage-driven verification strategies.
Expertise in creating reusable UVM-based test benches with VIPs and reference models.
Experience leveraging Large Language Models to enhance verification processes.
Hands-on experience with constraint random testing, SVA, and coverage-driven verification.
Skilled in Python-based automation solutions for design verification tasks.

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