Physical Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
18 days ago
Freshness
Confirmed live yesterday
Closes
Feb 20, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $187k
$130k most similar roles pay here $241k

This role pays more than 56% of similar roles. Most pay $157,800–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

The Physical Design Engineer joins the ASIC Products Division to develop next-generation products with a focus on parallel interfaces. This role involves the design implementation and physical layout of power grids, 2.5D and 3D die-die interconnects, as well as high-speed signal interconnects. The engineer will perform DRC, LVS, and electrical checking while performing electrical analysis and optimization of ubump and RDL patterns. Key responsibilities include automating common processes using TCL and Python scripting, evaluating new 2.5D and 3D interconnect technologies, and contributing to technology and testchip roadmapping for advanced packaging. The work centers on solving complex problems in machine learning, cloud computing, wireless infrastructure, and networking by developing interconnect technologies and IP for MCM, 2.5D, and 3D ICs. Candidates must possess expertise in various IC, Package, and PCB layout databases and tools.

What you'll do

  • Implement physical layouts for power grids and 2.5D/3D die-die interconnects.
  • Perform DRC, LVS, and electrical checking for integrated circuit designs.
  • Automate common design processes and routine tasks using TCL or Python scripting.
  • Develop high-speed signal interconnects in collaboration with SI and PI engineers.
  • Conduct electrical analysis and optimization of ubump and RDL patterns.
  • Evaluate and develop new 2.5D and 3D interconnect technologies.
  • Create technology and testchip roadmaps focused on advanced packaging.

What we're looking for

  • Bachelor's degree in Electrical Engineering or Computer Science and 12+ years related work experience.
  • Master's degree in Electrical Engineering or Computer Science and 10+ years related work experience.
  • Experience with various IC, Package, and PCB layout databases and tools.
  • Strong TCL and Python scripting experience to automate routine tasks.
  • Ability to perform physical layout implementation of power grids and 2.5D/3D die-die interconnects.
  • Ability to perform DRC, LVS, and electrical checking.
  • Experience in developing high-speed signal interconnects and performing electrical analysis for ubump and RDL patterns.
  • Capability to manage multiple concurrent customers under short timelines while working across a worldwide organization.

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