Physical Design Engineer

Broadcom

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Quick summary

Work type: On-site
Location: San Jose, CA
Employment: Full-time
Posted: 64 days ago
Freshness: Confirmed live today
Closes: Feb 20, 2027
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $198k

$140k $245k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $167,100–$229,575.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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The Physical Design Engineer joins the ASIC Products Division to develop next-generation products with a focus on parallel interfaces. This role involves the design implementation and physical layout of power grids, 2.5D and 3D die-die interconnects, and high-speed signal interconnects. Key responsibilities include performing DRC, LVS, and electrical checking, automating common design processes, and conducting electrical analysis and optimization of ubump and RDL patterns. The engineer will also evaluate new interconnect technologies and contribute to technology and testchip roadmapping for advanced packaging. Required skills include experience with IC, Package, and PCB layout databases and tools, along with strong TCL and Python scripting experience. The work addresses technical challenges in 3D and 2.5D interconnects for machine learning, cloud computing, and networking.

What does a Physical Design Engineer earn?

Median $177300 from 31 postings across 9 companies.

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Skills

Physical Layout 3D IC TCL Python DRC LVS Electrical Analysis SI PI RDL MCM PCB Layout Advanced Packaging

What you'll do

Design and implement physical layouts for power grids and 2.5D/3D die-die interconnects.
Perform DRC, LVS, and electrical checking on designs.
Automate common design processes and routine tasks using TCL and Python scripting.
Develop high-speed signal interconnects in coordination with SI and PI engineers.
Conduct electrical analysis and optimization of ubump and RDL patterns.
Evaluate and develop new 2.5D and 3D interconnect technologies.
Create technology and testchip roadmaps with a focus on advanced packaging.

What we're looking for

Bachelor's degree in Electrical Engineering or Computer Science and 12+ years related work experience.
Master's degree in Electrical Engineering or Computer Science and 10+ years related work experience.
Experience with various IC, Package, and PCB layout databases and tools.
Strong TCL and Python scripting experience to automate routine tasks.
Experience with physical layout implementation of power grids and 2.5D/3D die-die interconnects.
Ability to perform DRC, LVS, and electrical checking.
Experience developing high-speed signal interconnects alongside SI and PI engineers.
Ability to manage multiple concurrent customers under short timelines.

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