Packaging Design Engineer

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CASan Diego, CA
Salary
$200,000–$300,000 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Aug 3, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $172k
This role $250k
$109k most similar roles pay here $320k

This role pays more than 92% of similar roles. Most pay $146,000–$197,500 — the shaded band above. At the midpoint, this role pays about $250k versus about $172k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Packaging Design Engineer

The Packaging Design Engineer joins the AECG - Embedded Team to develop and optimize platforms for embedded and commercial applications across silicon, firmware, and software. Working within the Package group, this individual will manage multiple package families for FPGA devices by translating electrical requirements into cost-effective, manufacturable package technologies. Daily responsibilities include using Cadence tools for design, modeling, and simulations; performing Power Integrity analysis; conducting routing, stack-up, and component placement studies; and developing multi-signal models over 50 GHz bandwidth. The role requires proficiency in Cadence, Ansys, AutoCAD, and SKILL, along with knowledge of SerDes design, DFM/DFR, and organic technologies. This position solves critical hardware challenges by defining package requirements during project conception and collaborating with PCB Layout Engineers to optimize ballmaps and die sizes for high-performance, high-speed chips and systems.

What you'll do

  • Use Cadence tools to perform design modeling and simulations to ensure timely project sign-off.
  • Define package and module design requirements including technology, stack-up, and product specifications during conception stages.
  • Conduct routing, stack-up, and component placement studies for various device packaging.
  • Develop multi-signal package models over 50 GHz bandwidth with corresponding test structures for measurement correlation.
  • Perform Power Integrity analysis for core and IO to generate power delivery network requirements.
  • Create scripts to check package parameters across device families and maintain a database of electrical design guidelines.
  • Mentor junior package designers within the group.

What we're looking for

  • Bachelor's or Master's degree in Engineering.
  • Proficiency with Cadence package design tools is required.
  • Experience with 2D/3D package design and modeling tools like Ansys or AutoCAD.
  • Knowledge of organic and PCB technologies to interpret and negotiate layout guidelines.
  • Experience in high power, Gbps IO products.
  • Knowledge of SerDes design and package/PCB layout constraints.
  • Familiarity with DoE, DFM, and DFR processes.
  • Ability to mentor junior package designers within the group.

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