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Sr. IC Package Design Engineer (Silicon Engineering)

SpaceX

Austin, TX 2 days ago
Actively hiring Posted this week Verified listing
Cadence APD+/SIP SIWave HFSS ADS BGA Co-packaged Optics (CPO) Signal Integrity (SI) Power Integrity (PI) EM simulation Package design electrical review Substrate design RF Digital High-speed and mixed signal die Package/SIP layout
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Sr. IC Package Design Engineer (Silicon Engineering)

SpaceX

Irvine, CA 2 days ago $160,000–$225,000
Actively hiring Posted this week Verified listing Competitive pay
Cadence APD+/SIP SIWave HFSS ADS BGA Co-packaged Optics (CPO) Signal Integrity (SI) Power Integrity (PI) EM Simulation Package Design Electrical Review Substrate Design RFIC ASIC Manufacturing Reviews
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Package Design Engineer

Broadcom

San Jose, CA 5 days ago $141,300–$226,000
Actively hiring Posted this week Verified listing Above market
Cadence APD Allegro Package Designer Signal Integrity Power Integrity Flip-chip BGA SerDes HBM DDR5 Project Management Physical Design/Layout Package Engineering Design Automation Coding Co-design with external vendors Multi-time zone collaboration
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Package Design Engineer - Up to Staff level

Qualcomm

Santa Clara, CA 17 days ago $154,000–$252,800
Actively hiring Competitive pay
Cadence_APD SiP High_speed_IO_interfaces IC_packaging_structures Electromagnetic_field_analysis Flip_chip_BGA 2_5D_Interposer 3D_Interposer Cadence_Allegro PCB_Editor Advanced_Package_Designer XtractIM PowerSI HFSS Q3D Calibre_tool Design_Rules_Check High_speed_layout_constraints DDR PCIe UCIE
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IC Package/System Design solution Engineer, Staff

Qualcomm

San Diego, CA 103 days ago $154,000–$231,000
Actively hiring Competitive pay
ORCAD Allegro Valor ravel Python PERL TCL PCIe DDR Ethernet SerDes I2C I3C SPI MDIO SIPI PDN PMIC RF前端设计 内存技术 高速信号完整性分析 热管理 合规性测试
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