IP Verification Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CASan Diego, CAAustin, TXLongmont, CO
Salary: $200,000–$300,000 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Sep 1, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $250k

$132k $318k

below market most similar roles pay here above market

This role pays more than 86% of similar roles. Most pay $169,625–$241,750 — the blue band above. At the midpoint, this role pays about $250k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 510 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 510 roles with salary data.

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At a glance

TL;DR · IP Verification Engineer

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As an IP Verification Engineer within the AECG Group, you will join the front-end design and integration team to develop cutting-edge FPGA and ASIC products. You will collaborate with architects, hardware engineers, and firmware engineers to understand new features and ensure first pass silicon success. Your daily responsibilities include developing test plan documentation, coding IP or SS level UVM based testbenches, and building directed and random verification tests. You will run regressions and debug failures to ensure high functional, performance, and implementation quality. The role requires expertise in Verilog, SystemVerilog, Object Oriented programming, and UVM based verification frameworks. You should also possess skills in Python, Perl, and experience with PCIe, CXL, NVMe, or Ethernet protocols to solve complex IP architecture problems.

Skills

System Verilog Verilog UVM Python Perl FPGA ASIC PCIe CXL NVMe Ethernet Object Oriented Programming HLS Computer Architecture Simulation

What you'll do

Collaborate with architects and hardware engineers to understand new features for verification.
Develop comprehensive test plan documentation covering hardware, firmware, and software driver use cases.
Code IP or Subsystem level UVM based testbenches, monitors, scoreboards, and checkers.
Build directed and random verification tests for FPGA and ASIC designs.
Run regressions and debug test failures to ensure high design functional and performance quality.
Provide technical leadership to a small team through the project lifecycle from planning to tape out.
Maintain and edit scripts using Python or Perl to support verification processes.

What we're looking for

Bachelor's or Master's degree in computer engineering or Electrical Engineering.
Strong analytical and problem-solving skills with excellent communication skills.
Experience collaborating with engineers across different sites and time zones.
Ability to develop test plan documentation and code UVM-based testbenches and components.
Ability to build directed and random verification tests and run regressions.
Proficient in IP level verification (preferred).
Proven record of providing technical leadership to a small team through project lifecycle (preferred).
Expert in Verilog, SystemVerilog, Object Oriented programming, and UVM based verification frameworks (preferred).

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