Lead Electrical Engineering FPGA Verification Engineer

L3Harris

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Palm Bay, FL
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $192k

$137k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $168,500–$216,250.

Based on 240 similar postings.

Employer

About L3Harris

L3Harris Technologies is a US aerospace and defense technology company providing space and airborne systems, communications, electronic warfare, and missile propulsion solutions for government and commercial customers.

L3Harris currently has 550 open roles on FindRole.

Listed pay typically runs $106,500–$197,500 across 211 roles with salary data.

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At a glance

TL;DR · Lead Electrical Engineering FPGA Verification Engineer

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Lead, Electrical Engineering - FPGA Verification Engineer joins the engineering team to develop and execute verification plans for complex digital designs. The role involves architecting UVM test cases for individual blocks, building reusable agents, top-level testbench modules, and environments while defining functional coverage models based on design requirements. Day-to-day responsibilities include debugging simulation failures, analyzing coverage metrics, and collaborating with design and systems engineers to ensure functional correctness throughout the development lifecycle. The position requires expertise in SystemVerilog, SystemVerilog Assertions, and Object Oriented Programming concepts, alongside proficiency in scripting languages like Python, Perl, or bash within Linux environments. Candidates will work with EDA tools such as Vivado or Quartus to verify FPGA architectures involving high-speed serial protocols like PCI Express and Ethernet, while addressing technical challenges related to network-centric designs and memory interfaces.

Skills

UVM SystemVerilog FPGA Xilinx Altera Vivado Quartus Python C++ VHDL PCI Express Ethernet SRIO Linux Git SVN Bash Perl DO-254

What you'll do

Develop and execute comprehensive FPGA verification plans to ensure design integrity.
Architect UVM test cases for individual blocks and sub-blocks within an FPGA.
Build reusable UVM components including agents, top-level testbench modules, and environments.
Create drivers, monitors, predictors, and scoreboards based on specific DUT requirements.
Define and implement functional coverage models to meet design requirements and close code coverage.
Debug simulation failures and identify corner cases to improve design robustness.
Utilize SystemVerilog and assertion-based verification to validate complex digital designs.
Automate regression testing and manage verification environments using scripting languages like Python or Perl.

What we're looking for

Bachelor's degree and 9 years of experience, a graduate degree and 7 years of experience, or no degree and 13 years of experience.
Ability to obtain U.S. government clearance (must be a U.S. citizen).
Experience developing and executing verification plans and building reusable UVM-based testbenches for complex digital designs.
Proficiency in SystemVerilog, assertion-based verification, and Object Oriented Programming concepts.
Familiarity with FPGA design processes, including requirements generation, peer reviews, and integration testing.
Proficiency in scripting languages such as bash/csh, Perl, or Python.
Experience with Altera or Xilinx/AMD FPGA architectures and Vivado or Quartus tool suites (preferred).
Security clearance.

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