IC Verification Engineer

Broadcom

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Employment
Full-time
Posted
64 days ago
Freshness
Confirmed live yesterday
Closes
Feb 20, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $196k
$137k $235k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,500–$223,000.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · IC Verification Engineer

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The IC Verification Engineer will join the team to architect and develop scalable, reusable testbench environments using standard verification methodologies. The role involves driving test plans for Block, Core, and SOC features, writing functional coverage, and building pseudo-random tests to achieve full coverage and verification closure. Key responsibilities include debugging regression failures, analyzing coverage gaps, mentoring junior engineers, and leading documentation for verification strategies. Candidates must be proficient in SystemVerilog and methodologies like UVM or VMM. The position requires experience with complex protocols such as PCI Express or AXI. Technical skills in Python, Perl, and Makefiles are also valued. This role focuses on the full ASIC cycle from architecture development to tapeout, ensuring high-quality verification of complex designs and multi-layered protocols.

Skills

System Verilog UVM VMM ASIC PCIe AXI Python Perl Makefiles Functional Coverage Verification Methodologies

What you'll do

  • Architect and develop scalable and reusable Testbench environments using standard Verification Methodologies.
  • Drive test plans for Block, Core, and SOC features and write functional coverage.
  • Build pseudo-random tests to achieve full functional coverage and bring verification to closure.
  • Debug regression failures and analyze functional coverage gaps to improve test coverage.
  • Lead the documentation of verification strategies, including test plans and verification environments.
  • Lead reviews with design and architecture teams to ensure verification quality.
  • Mentor junior team members and guide their technical development.

What we're looking for

  • Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience.
  • Master's degree in Electrical/Electronics/Equivalent with 10+ years of experience.
  • 10+ years of experience in developing complex Verification Environments, Test plans, Functional coverage, and pseudo-random testing.
  • Experience completing a full ASIC cycle from Architecture development to Tapeout with a focus on Verification.
  • Proficiency in SystemVerilog and Verification Methodologies like UVM/VMM.
  • Ability to debug regression failures and understand complex designs.
  • Understanding of a complex protocol like PCI Express or other multi-layered protocols.
  • Scripting knowledge of Python or Perl (preferred); experience with PCIe protocol (preferred); experience with AXI (preferred).

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