IC Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
18 days ago
Freshness
Confirmed live yesterday
Closes
Feb 20, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $186k
This role $187k
$126k most similar roles pay here $241k

This role pays more than 60% of similar roles. Most pay $159,937–$212,500 — the shaded band above. At the midpoint, this role pays about $187k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · IC Verification Engineer

As an IC Verification Engineer, you will join the team to architect and develop scalable, reusable testbench environments using established verification methodologies. Your daily responsibilities include driving test plans for block, core, and SOC features, writing functional coverage, and building pseudo-random tests to achieve full coverage and closure. You will debug regression failures, analyze coverage gaps, mentor junior engineers, and lead the documentation of verification strategies while collaborating with design and architecture teams. The role requires expertise in SystemVerilog and UVM or VMM methodologies to verify complex designs throughout a full ASIC cycle from architecture to tapeout. You must possess deep knowledge of multi-layered protocols like PCI Express. Preferred skills include Python or Perl scripting, experience with Makefiles, and familiarity with AXI protocols to ensure high verification quality and efficiency for the hardware products.

What you'll do

  • Architect and develop scalable, reusable testbench environments using UVM or VMM methodologies.
  • Drive comprehensive test plans for all features across Block, Core, and SOC levels.
  • Write functional coverage goals and build pseudo-random tests to achieve full verification closure.
  • Debug regression failures and analyze functional coverage gaps to improve test coverage.
  • Lead the documentation of verification strategies, including test plans and environment specifications.
  • Lead technical reviews with design and architecture teams to ensure quality and efficiency.
  • Mentor junior team members and provide guidance on verification best practices.

What we're looking for

  • Bachelor's degree in Electrical/Electronics or equivalent with 12+ years of experience, or a Master's degree with 10+ years of experience.
  • 10+ years of experience in developing complex Verification Environments, Test plans, Functional coverage, and pseudo-random testing.
  • Experience completing a full ASIC cycle from Architecture development to Tapeout with a focus on Verification.
  • Proficiency in SystemVerilog and verification methodologies such as UVM or VMM.
  • Strong debug skills for analyzing regression failures and understanding complex designs.
  • Understanding of complex multi-layered protocols like PCI Express.
  • Ability to mentor junior engineers and work collaboratively with the team.
  • Experience with PCIe protocol, Python/Perl scripting, Makefiles, or AXI protocols (preferred).

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