Integration Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $126,800–$190,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $157k

This role $159k

$116k most similar roles pay here $200k

This role pays more than 56% of similar roles. Most pay $126,237–$186,862 — the shaded band above. At the midpoint, this role pays about $159k versus about $157k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Integration Engineer

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The Integration Engineer role within the Hardware team requires a candidate with 0 to 2 years of experience in SoC design. This position involves integrating third-party or internal IP blocks, managing RTL codebases, and ensuring proper bus interface protocols are implemented. Day-to-day responsibilities include creating top-level SoC RTL, developing automated build systems, defining synthesis constraints, and collaborating closely with physical design teams for timing closure. The ideal candidate should have a solid understanding of digital logic design using SystemVerilog or Verilog, familiarity with Synopsys and Cadence tools, experience with bus protocols like AXI and AHB, and strong scripting skills in Python, Perl, TCL, or Shell for automation tasks.

Skills

SystemVerilog Verilog Synopsys Cadence AXI AHB APB PCIe USB DDR Python Perl TCL Shell Lint Synthesis CDC RDC DFT STA

What you'll do

Integrate third-party or internal IP blocks into a SoC.
Manage RTL codebases to ensure correct connectivity and bus protocols.
Create and maintain top-level SoC RTL, wrappers, and interconnects.
Run linting and synthesis tools to debug and validate design quality.
Develop automated build and regression systems for integration processes.
Define and validate synthesis and timing constraints (SDC files).
Work with physical design teams to achieve timing closure at the top level.

What we're looking for

Bachelor's Degree with relevant experience in digital logic design.
Proficient in SystemVerilog/Verilog for RTL development.
Experience with SoC design flows, tools (Synopsys, Cadence).
Knowledge of bus protocols (AXI, AHB) and interface standards (PCIe, USB).
Expertise in ASIC tool flows including linting, synthesis, CDC, DFT, STA.
Strong scripting skills for automation (Python, Perl, TCL, Shell).
Excellent communication and cross-functional collaboration abilities.

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