Integration Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $129,300–$194,700 / yr
Posted: 143 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $170k

This role $162k

$121k most similar roles pay here $209k

This role pays less than 55% of similar roles. Most pay $138,920–$200,700 — the shaded band above. At the midpoint, this role pays about $162k versus about $170k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Integration Engineer

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As an Integration Engineer, you will join a complex hardware team focused on crafting upcoming products and transforming hardware technology. You will be responsible for ASIC design tasks including integrating third-party or internal IP blocks like CPUs and GPUs into a SoC, managing RTL codebases, and ensuring correct bus and interface protocols such as AMBA, AXI, AHB, PCIe, USB, and DDR. Your daily work involves creating top-level SoC RTL, running linting and synthesis, defining SDC timing constraints, and achieving timing closure with physical design teams. You will also develop automated build and regression systems and provide functional verification support. The role requires proficiency in SystemVerilog, Verilog, and scripting languages like Python, Perl, TCL, and Shell, while utilizing industry tools from Synopsys or Cadence to solve complex hardware integration challenges.

Skills

ASIC Design SystemVerilog Verilog RTL SoC AMBA AXI AHB APB PCIe USB DDR Python Perl TCL Shell Synopsys Cadence Linting Synthesis CDC DFT STA SDC

What you'll do

Integrate third-party and internal IP blocks into the SoC architecture.
Manage and merge RTL codebases while ensuring correct bus and interface protocols.
Create and maintain top-level SoC RTL, wrappers, and interconnects.
Run and debug linting, CDC/RDC, and logic synthesis to ensure design quality.
Develop and maintain automated build and regression systems for integration.
Define and validate synthesis and timing constraints using SDC files.
Collaborate with physical design and STA teams to achieve top-level timing closure.
Provide functional verification support including simulation bring-up and debug.

What we're looking for

Bachelor's Degree is required.
Experience in ASIC design including IP integration, RTL management, and top-level assembly.
Proficiency in digital logic design and RTL development using SystemVerilog or Verilog.
Familiarity with SoC design flows and tools from vendors like Synopsys or Cadence.
Knowledge of bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR).
Experience with ASIC tool flows including lint, synthesis, CDC, DFT, and STA.
Strong scripting skills in Python, Perl, TCL, or Shell for automation.
Ability to perform debugging, problem-solving, and cross-functional collaboration.