ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 22 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 94% of similar roles. Most pay $165,550–$216,250 — the shaded band above. At the midpoint, this role pays about $255k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer, Silicon Security

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As an ASIC Design and Integration Engineer – Silicon Security, you will join the Silicon Security team to build secure subsystems protecting the SoC. You will be responsible for the micro-architecture, RTL design, and integration of security features such as cryptographic engines, side channel attack monitors, and data protection logics. Your daily work involves architecting high performance, area, and power efficient RTL blocks while integrating security IPs into subsystems to meet timing and functionality requirements. You will drive front-end quality flows from RTL to netlist using Lint, CDC/RDC analysis, UPF development, synthesis, and AI-assisted tools. The role requires expertise in Verilog or SystemVerilog, AMBA bus protocols like AXI, AHB, and APB, as well as knowledge of cryptography, key management, and physical attack countermeasures to protect sensitive data from complex side channel attacks.

Skills

RTL Verilog SystemVerilog ASIC Design Synthesis Timing Closure CDC RDC UPF AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist Hardware Security

What you'll do

Architect and design state-of-the-art security features and hardware defenses against side channel attacks.
Develop high-performance, area-efficient RTL blocks for secure subsystems.
Integrate security IPs into subsystems while ensuring timing, performance, and security requirements are met.
Resolve integration issues across multiple IP blocks and coordinate with owners on interface concerns.
Drive front-end quality flows from RTL to netlist including Lint, CDC/RDC analysis, and Synthesis.
Develop UPF for low-power design implementation.
Utilize AI-assisted tools to enhance design quality and productivity.

What we're looking for

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
10 years of industry experience.
10 years of RTL design experience using Verilog or SystemVerilog.
Experience with CDC and RDC analysis and verification (preferred).
Familiarity with low-power design techniques and UPF (preferred).
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability (preferred).
Background in cryptography and cryptographic algorithm implementation (preferred).
Experience with hardware security concepts, AMBA bus protocols, and clock/reset architecture (preferred).

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 32 days ago $129,300–$194,700

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification CDC RDC PPA Micro-architecture Digital Design

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