ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 68 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $164,938–$216,562 — the blue band above. At the midpoint, this role pays about $255k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer, Silicon Security

Role Posting Log in to save

The ASIC Design and Integration Engineer – Silicon Security joins the Silicon Security team to build secure subsystems protecting the entire Apple SoC. This role involves the micro-architecture, RTL design, and integration of secure subsystems, including cryptographic engines, side channel attack monitors, and data protection logics. The engineer will architect security features, integrate security IPs, and resolve integration issues across multiple IP blocks while ensuring timing, performance, and security requirements are met. Key responsibilities include driving front-end quality flows from RTL to netlist using Lint, CDC/RDC analysis, UPF development, timing, and Synthesis. Required skills include Verilog or SystemVerilog for RTL design, knowledge of AMBA protocols like AXI, AHB, and APB, and experience with low-power design techniques to prevent complex side channel attacks.

Skills

Verilog SystemVerilog RTL Design ASIC Design AMBA AXI AHB APB CDC RDC Lint Synthesis UPF Timing Closure Cryptography Low-Power Design Finite State Machines Pipelining

What you'll do

Architect and design state-of-the-art security features and hardware defenses.
Develop high-performance, area, and power-efficient RTL blocks for secure subsystems.
Integrate security IPs into subsystems while meeting timing, performance, and security requirements.
Resolve integration issues across multiple IP blocks and coordinate on interface concerns.
Drive front-end quality flows from RTL to netlist, including Lint and CDC/RDC analysis.
Develop UPF and perform synthesis and timing closure for designs.
Utilize AI-assisted tools to improve design quality and productivity.

What we're looking for

Bachelor's degree in Electrical Engineering, Computer Engineering, or a relevant field.
10 years of industry experience.
10 years of RTL design experience using Verilog or SystemVerilog.
Experience with CDC and RDC analysis and verification (preferred).
Experience with lint, synthesis, and timing closure (preferred).
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
Familiarity with low-power design techniques (preferred).
Background in cryptography and cryptographic algorithm implementations (preferred).

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