ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $129,300–$194,700 / yr
Posted: 84 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $162k

$117k $242k

below market most similar roles pay here above market

This role pays less than 76% of similar roles. Most pay $167,346–$217,500 — the blue band above. At the midpoint, this role pays about $162k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer, Silicon Security

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The ASIC Design and Integration Engineer – Silicon Security joins the Silicon Security team to build secure subsystems protecting the entire Apple SoC. This role involves the micro-architecture, RTL design, and integration of hardware defenses designed to prevent complex side channel attacks and ensure data integrity. Key responsibilities include architecting security features, integrating security IPs, and driving front-end quality flows from RTL to netlist. The engineer will perform hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis while leveraging AI-assisted tools. Required skills include RTL design using Verilog or SystemVerilog, knowledge of finite state machines, pipelining, and digital design fundamentals like timing closure. Candidates should also be familiar with AMBA bus protocols, low-power design techniques, and cryptographic algorithm implementations.

Skills

RTL Design Verilog SystemVerilog ASIC Design Micro-architecture Synthesis Timing Closure CDC RDC Lint UPF AMBA AXI AHB APB Cryptography Low-power Design Front-end Quality Flows

What you'll do

Architect and design state-of-the-art security features and RTL blocks.
Integrate security IPs into secure subsystems while meeting timing and performance requirements.
Resolve integration issues across multiple IP blocks and coordinate with IP owners.
Drive front-end quality flows from RTL to netlist including Lint and CDC/RDC analysis.
Develop UPF and perform synthesis and timing closure for secure subsystems.
Utilize AI-assisted tools to improve design quality and productivity.

What we're looking for

BS in Electrical Engineering, Computer Engineering, or a relevant field.
0 years of experience.
Solid RTL design experience using Verilog or SystemVerilog including finite state machines and pipelining (preferred).
Strong problem-solving and collaboration skills (preferred).
Solid understanding of digital design fundamentals including CDC, synthesis, and timing closure (preferred).
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
Familiarity with low-power design techniques (preferred).
Background in cryptography and cryptographic algorithm implementations (preferred).