ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $129,300–$194,700 / yr
Posted: 38 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $162k

$117k most similar roles pay here $242k

This role pays less than 76% of similar roles. Most pay $167,112–$216,562 — the shaded band above. At the midpoint, this role pays about $162k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer, Silicon Security

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As an ASIC Design and Integration Engineer – Silicon Security, you will join the Silicon Security team to build secure subsystems that protect the SoC from complex side channel attacks while ensuring data integrity. You will be responsible for the micro-architecture, RTL design, and integration of security features, including cryptographic engines and data protection logics. Your daily work involves architecting high performance, area, and power efficient RTL blocks, resolving integration issues across multiple IP blocks, and driving front-end quality flows from RTL to netlist. You will utilize Verilog or SystemVerilog for design, perform CDC and RDC analysis, develop UPF, and manage synthesis and timing closure. The role requires expertise in AMBA bus protocols, low-power techniques, and hardware security concepts like key management and physical attack countermeasures to secure consumer electronics.

Skills

RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-power Design Lint Netlist Hardware Security

What you'll do

Architect and design state-of-the-art security features for the SoC.
Develop high-performance, area-efficient RTL blocks for secure subsystems.
Integrate security IPs while ensuring timing, performance, and security requirements are met.
Resolve integration issues across multiple IP blocks and coordinate with owners on interface concerns.
Drive front-end quality flows from RTL to netlist including Lint, CDC/RDC, and Synthesis.
Develop UPF for low-power design implementation.
Utilize AI-assisted tools to enhance design quality and productivity.

What we're looking for

Bachelor of Science in Electrical Engineering, Computer Engineering, or a related field.
Experience with RTL design using Verilog or SystemVerilog.
Experience with CDC and RDC analysis and verification.
Familiarity with low-power design techniques and UPF development.
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
Background in cryptography and cryptographic algorithm implementation.
Experience with hardware security concepts such as key management and physical attack countermeasures.
Strong knowledge of AMBA bus protocols including AXI, AHB, and APB.