Integration Engineer

What you'll do

• Integrate third-party and internal IP blocks into a System on Chip (SoC).
• Merge RTL codebases and ensure correct implementation of bus and interface protocols.
• Create and maintain top-level SoC RTL, wrappers, and interconnects.
• Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality.
• Develop and maintain automated build and regression systems for integration.
• Define and validate synthesis and timing constraints using SDC files.
• Work with physical design and STA teams to achieve top-level timing closure.
• Provide simulation bring-up and debug support to design verification teams.

What we're looking for

• 10+ years of experience.
• Experience in ASIC design including IP integration, RTL integration, and top-level assembly.
• Experience running and debugging lint, CDC/RDC, and logic synthesis.
• Experience developing automated build and regression systems for integration.
• Experience defining and validating synthesis and timing constraints (SDC files).
• Solid understanding of digital logic design and RTL development in SystemVerilog and Verilog (preferred).
• Familiarity with SoC design flows, bus protocols, and scripting languages like Python, Perl, or TCL (preferred).
• Bachelor's Degree.