Integration Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $184,700–$324,800 / yr
Posted: 42 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $169k

This role $255k

$106k most similar roles pay here $348k

This role pays more than 98% of similar roles. Most pay $138,583–$200,000 — the shaded band above. At the midpoint, this role pays about $255k versus about $169k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Integration Engineer

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As an Integration Engineer, you will join a complex hardware team focused on crafting upcoming products and transforming hardware technology. You will be responsible for ASIC design tasks including integrating third-party or internal IP blocks like CPU, GPU, and memory controllers into a SoC. Your daily work involves managing and merging RTL codebases, ensuring correct bus and interface protocols such as AMBA, AXI, AHB, PCIe, USB, and DDR are implemented. You will create top-level SoC RTL, manage linting, synthesis, and timing constraints via SDC files, and develop automated build and regression systems. The role requires proficiency in SystemVerilog, Verilog, and scripting languages like Python, Perl, TCL, and Shell. You will also provide functional verification support, perform debug, and collaborate with physical design teams to achieve top-level timing closure for complex hardware designs.

Skills

ASIC Design SystemVerilog Verilog RTL SoC AMBA AXI AHB APB PCIe USB DDR Python Perl TCL Shell Synopsys Cadence Linting Synthesis CDC DFT STA SDC

What you'll do

Integrate third-party and internal IP blocks into a System on Chip (SoC).
Manage and merge RTL codebases while ensuring correct bus and interface protocol implementation.
Create and maintain top-level SoC RTL, wrappers, and interconnects.
Run and debug linting, CDC/RDC, and logic synthesis to ensure design quality.
Develop and maintain automated build and regression systems for integration.
Define and validate synthesis and timing constraints using SDC files.
Collaborate with physical design and STA teams to achieve top-level timing closure.
Provide functional verification support including simulation bring-up and debug.

What we're looking for

Bachelor's Degree is required.
Candidates must have at least 10 years of experience.
Experience in ASIC design including IP integration, RTL management, and top-level assembly is required.
Proficiency in digital logic design and RTL development using SystemVerilog or Verilog is preferred.
Familiarity with SoC design flows and tools such as Synopsys or Cadence is preferred.
Knowledge of bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR) is preferred.
Experience with ASIC tool flows including lint, synthesis, CDC, DFT, and STA is preferred.
Strong scripting skills in Python, Perl, TCL, or Shell for automation are preferred.

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