Integration Engineer

What you'll do

• Integrate third-party and internal IP blocks into a System on Chip (SoC).
• Manage and merge RTL codebases while ensuring correct bus and interface protocol implementation.
• Create and maintain top-level SoC RTL, wrappers, and interconnects.
• Run and debug linting, CDC/RDC, and logic synthesis to ensure design quality.
• Develop and maintain automated build and regression systems for integration.
• Define and validate synthesis and timing constraints using SDC files.
• Collaborate with physical design and STA teams to achieve top-level timing closure.
• Provide functional verification support including simulation bring-up and debug.

What we're looking for

• Bachelor's Degree and at least 3 years of experience.
• Experience in ASIC design including IP integration, RTL management, and top-level assembly.
• Proficiency in digital logic design and RTL development using SystemVerilog or Verilog.
• Familiarity with SoC design flows and tools from vendors like Synopsys or Cadence.
• Knowledge of bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR).
• Experience with ASIC tool flows including lint, synthesis, CDC, DFT, and STA.
• Strong scripting skills in Python, Perl, TCL, or Shell for automation.
• Ability to perform debugging, problem-solving, and cross-functional collaboration.