Integration Engineer

Apple Inc

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$150,400–$277,600 / yr
Posted
127 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $171k
This role $214k
$110k $296k
below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $127,887–$214,000 — the blue band above. At the midpoint, this role pays about $214k versus about $171k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Integration Engineer

The Integration Engineer joins a complex hardware team to craft upcoming products by transforming hardware technology. This role focuses on ASIC design, specifically integrating third-party and internal IP blocks like CPUs, GPUs, and memory controllers into a System on Chip. The engineer will manage and merge RTL codebases, ensure connectivity for bus protocols such as AMBA, AXI, AHB, APB, PCIe, USB, and DDR, and create top-level SoC RTL, wrappers, and interconnects. Key responsibilities include running lint, CDC/RDC, and logic synthesis, defining SDC timing constraints, and achieving timing closure. The position requires proficiency in SystemVerilog, Verilog, and scripting languages like Python, Perl, TCL, and Shell. The engineer will also develop automated build and regression systems while providing functional verification support for simulation bring-up and debug.

What you'll do

  • Integrate third-party and internal IP blocks into a System-on-Chip (SoC).
  • Merge RTL codebases while ensuring correct connectivity and bus interface protocols.
  • Create and maintain top-level SoC RTL, wrappers, and interconnects.
  • Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality.
  • Develop and maintain automated build and regression systems for integration.
  • Define and validate synthesis and timing constraints using SDC files.
  • Work with physical design and STA teams to achieve top-level timing closure.
  • Provide simulation bring-up and debug support to design verification teams.

What we're looking for

  • Bachelor's Degree with 3+ years of experience.
  • Experience integrating third-party or internal IP blocks into a SoC.
  • Experience managing and merging RTL codebases and ensuring bus/interface protocol connectivity.
  • Experience creating and maintaining top-level SoC RTL, wrappers, and interconnects.
  • Experience running and debugging lint, CDC/RDC, and logic synthesis.
  • Experience developing and maintaining automated build and regression systems for integration.
  • Experience defining and validating synthesis and timing constraints (SDC files).
  • Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR) (preferred).

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