Integration Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $147,400–$272,100 / yr
Posted: 5 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $147k

This role $210k

$93k most similar roles pay here $291k

This role pays more than 88% of similar roles. Most pay $114,925–$178,318 — the shaded band above. At the midpoint, this role pays about $210k versus about $147k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1817 open roles on FindRole.

Listed pay typically runs $163,300–$272,100 across 1482 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Integration Engineer

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The Integration Engineer role within the Hardware team requires a candidate with 3+ years of experience to integrate third-party or internal IP blocks into SoCs, manage RTL codebases, and ensure proper bus interface protocols. Day-to-day responsibilities include creating top-level SoC RTL, developing automated build systems, defining synthesis constraints, and collaborating closely with physical design teams for timing closure. The ideal candidate will have a solid understanding of digital logic design using SystemVerilog or Verilog, familiarity with Synopsys and Cadence tools, and experience with bus protocols like AXI and AHB. Strong scripting skills in Python, Perl, TCL, or Shell are essential for automation tasks, while excellent communication and cross-functional collaboration abilities are crucial for success in this high-scale SoC design environment.

Skills

SystemVerilog Verilog Synopsys Cadence AXI AHB APB PCIe USB DDR Python Perl TCL Shell Lint Synthesis CDC DFT STA

What you'll do

Integrate third-party or internal IP blocks into a SoC.
Manage RTL codebases to ensure correct connectivity and bus protocols.
Create and maintain top-level SoC RTL, wrappers, and interconnects.
Develop automated build and regression systems for integration processes.
Define and validate synthesis and timing constraints (SDC files).
Work with physical design teams to achieve timing closure at the top level.
Provide functional verification support including simulation bring-up and debug.

What we're looking for

3+ years of experience in digital logic design and RTL development.
Proficiency in SystemVerilog or Verilog for hardware description.
Experience with SoC integration, including bus protocols (AXI, AHB) and interface standards (PCIe, USB).
Knowledge of ASIC tool flows: linting, synthesis, CDC, DFT, STA.
Strong scripting skills in Python, Perl, TCL, or Shell for automation.
Excellent debugging and problem-solving abilities.

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