ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$277,600 / yr
Posted: 38 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $214k

$135k most similar roles pay here $293k

This role pays more than 69% of similar roles. Most pay $165,550–$216,562 — the shaded band above. At the midpoint, this role pays about $214k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer, Silicon Security

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As an ASIC Design and Integration Engineer – Silicon Security, you will join the Silicon Security team to build secure subsystems that protect the SoC from complex side channel attacks while ensuring data integrity. You will be responsible for the micro-architecture, RTL design, and integration of security features, including cryptographic engines, side channel attack monitors, and data protection logics. Your daily work involves architecting high performance, area, and power efficient RTL blocks, resolving integration issues across multiple IP blocks, and driving front-end quality flows from RTL to netlist. You will utilize Verilog or SystemVerilog, manage CDC/RDC analysis, perform UPF development, and use AI-assisted tools for design productivity. The role requires expertise in AMBA bus protocols, low-power design techniques, timing closure, and hardware security concepts like key management and physical attack countermeasures.

Skills

RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist

What you'll do

Architect and design state-of-the-art security features including cryptographic engines and side channel attack monitors.
Develop high-performance, area-efficient RTL blocks for secure subsystems.
Integrate security IPs into the subsystem while ensuring timing, performance, and security requirements are met.
Resolve integration issues across multiple IP blocks and coordinate with owners on interface concerns.
Drive front-end quality flows from RTL to netlist including Lint, CDC/RDC analysis, and Synthesis.
Develop UPF for low-power design implementation.
Utilize AI-assisted tools to enhance design quality and productivity.

What we're looking for

BS in Electrical Engineering, Computer Engineering, or a related field.
3 years of industry experience.
3 years of RTL design experience using Verilog or SystemVerilog.
Experience with CDC and RDC analysis and verification.
Familiarity with low-power design techniques and UPF.
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
Background in cryptography and cryptographic algorithm implementation.
Experience with hardware security concepts such as key management and physical attack countermeasures.

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 32 days ago $129,300–$194,700

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification CDC RDC PPA Micro-architecture Digital Design

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