ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$277,600 / yr
Posted: 84 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $164,938–$217,500 — the blue band above. At the midpoint, this role pays about $214k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer, Silicon Security

Role Posting Log in to save

The ASIC Design and Integration Engineer – Silicon Security joins the Silicon Security team to build secure subsystems protecting the entire Apple SoC. This role involves the micro-architecture, RTL design, and integration of hardware defenses designed to prevent complex side channel attacks and ensure data integrity. Key responsibilities include architecting security features, integrating security IPs, and driving front-end quality flows from RTL to netlist. The engineer will perform hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis while leveraging AI-assisted tools. Required skills include Verilog or SystemVerilog, and knowledge of AMBA bus protocols like AXI, AHB, and APB. The work focuses on cryptographic engines, side channel attack monitors, and data protection logics to secure sensitive information across the product line.

Skills

RTL Design Verilog SystemVerilog ASIC Design Synthesis Timing Closure UPF CDC RDC Lint AMBA AXI AHB APB Cryptography Hardware Security Low-Power Design Netlist

What you'll do

Architect and design state-of-the-art security features and RTL blocks for secure subsystems.
Integrate security IPs into subsystems while meeting timing, performance, and security requirements.
Resolve integration issues across multiple IP blocks and coordinate with owners on interface concerns.
Drive front-end quality flows from RTL to netlist, including Lint, CDC/RDC analysis, and Synthesis.
Develop UPF and manage timing closure for low-power design requirements.
Implement cryptographic engines and hardware defenses against side-channel attacks.
Utilize AI-assisted tools to improve design quality and engineering productivity.

What we're looking for

BS in Electrical Engineering, Computer Engineering, or a relevant field.
3 years of industry experience.
3 years of RTL design experience using Verilog or SystemVerilog.
Experience with CDC and RDC analysis and verification (preferred).
Familiarity with low-power design techniques and UPF (preferred).
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability (preferred).
Background in cryptography and cryptographic algorithm implementation (preferred).
Experience with hardware security concepts, key management, and AMBA bus protocols (preferred).

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