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GPU Physical Design Clocking Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
ASIC Integration Physical Design Clock Distribution Floorplanning P&R Flows Timing Verification Netlist to Tapeout PPA ESD Solutions Design for Yield Manufacturability multi Vt strategies GPU Architecture
10+ yrs exp
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GPU Physical Design Clocking Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today High trust
ASIC Integration Physical Design Clock Distribution Floorplanning P&R Flows Timing Verification Netlist to Tapeout PPA ESD Solutions Design for Yield Manufacturability Multi Vt Strategies IP Integration
10+ yrs exp
Save

CPU RTL Power, Clocking, Reset Design Engineer

Amd

Fort Collins, CO 42 days ago $144,800–$217,200
Actively hiring Confirmed live today High trust Below market
RTL Design Verilog HDL Microarchitecture clock-domain crossing Power Management Voltage Management Scripting Tapeout Closure Design-for-Test Physical Design Control Fabric
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