Custom IC Layout Engineer

What you'll do

• Perform cell and block layout of Analog and Mixed-Signal circuit functions.
• Implement circuit layout strategies to meet area, performance, and power goals.
• Support IC floor planning and place & route for full chip digital designs.
• Execute parasitic extraction of circuit layout and iterate on design improvements.
• Craft reusable scripts and methodologies to automate design flow and increase efficiency.
• Execute project tape out verification including DRC, ERC, and LVS.
• Create and present design documentation for internal design reviews.
• Provide schedule and cost inputs to program management.

What we're looking for

• BSEE or relevant years of experience.
• 5+ years of experience performing custom layout.
• Strong working knowledge of custom transistor-level layout and matching techniques.
• Strong working knowledge of Cadence Virtuoso (Layout and Schematic) and Mentor/Siemens Calibre tool suites.
• Proficiency in scripting and automation using TCL, SKILL, Perl, Python, and Shell scripts in a Linux environment.
• Experience executing project tape out verification including DRC, ERC, and LVS.
• Extensive understanding of signal integrity, reliability, layout effects (EM, IR drop), and foundry DFM requirements.
• Track record of custom layout experience for designs such as SRAM, IO, PLLs, ADCs, and amplifiers.
• Detailed understanding of 22nm and below CMOS foundry design node rules (preferred).
• Experience with both Analog and Memory layouts (preferred).
• Knowledge of ASIC IC test and characterization (preferred).
• Understanding of digital design and place and route principles (preferred).